US5115499A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Shared computer resource allocation system having apparatus for informing a requesting computer of the identity and busy/idle status of shared resources by command code
Assignee: Radisys Corp
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Filing: 1991-01-02
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Granted: 1992-05-19
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Expires: 2011-01-02
Abstract
Abstract Computer system resources shared by several central processing units are allocated by allowing one processing unit to temporarily gain exclusive access to a particular shared resource. Access to a particular resource is controlled by a memory location which contains information representing the current state of the resource and the identity of any processing element currently utilizing the resource. In the case where several resources are interchangeable, the memory location may also contain information regarding the busy/idle states of other interchangeable resources. The memory location can be interrogated by any of the processing elements via command and address information. If the contents of the memory location indicate that the associated resource is not in use, then the interrogating processing element immediately obtains control of the resource. If the resource is in use, the identity of the processing element currently using the resource and any stored resource state information is returned to the interrogating processing element which can then continue processing without the resource or choose another idle resource.
Inventors
- 👤 Jack J. Stiffler
- 👤 James M. Nolan
- 👤 Peter Mark
- 👤 David Harvey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/52
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
307 words
In a computer system comprising: a plurality of data processing elements, each of said plurality f data processing elements being capable of sequentially executing a plurality of data processing tasks; a processor bus connected to each of said plurality of data processing elements for receiving signals from, and transmitting signals to, said data processing elements; a system bus; first interface means for connecting said processor bus to said system bus; a plurality of shared system resources, each of said plurality of shared resources having a busy and an idle status; a peripheral bus connected to each of said plurality of shared resources; second interface means for connecting said peripheral bus to said system bus; a memory location in one of said plurality of shared resources; means for selecting one of said plurality of data processing elements for performing one of said plurality of processing tasks, said selected data processing element including means for generating command codes; lock status circuitry in said one shared resources responsive to a first command code generated by said selected data processing element for returning to said selected data processing element a status code stored in said memory location, said status code indicating to said selected processing element the busy and idle status of each of said plurality of shared system resources; and lock update circuitry in said one shared resource responsive to a second command code generated by said selected data processing element for storing in said memory location an identifying code identifying one of said plurality of shared system resources which said selected data processing element can use for a subsequent data processing task, said identifying code being calculated in a predetermined manner from said command code and a status code stored in said memory location indicating the busy and idle status of each of said plurality of shared system resources.
Claim 2
Dependent Claim
307 words
In a computer system comprising: a plurality of data processing elements, each of said plurality f data processing elements being capable of sequentially executing a plurality of data processing tasks; a processor bus connected to each of said plurality of data processing elements for receiving signals from, and transmitting signals to, said data processing elements; a system bus; first interface means for connecting said processor bus to said system bus; a plurality of shared system resources, each of said plurality of shared resources having a busy and an idle status; a peripheral bus connected to each of said plurality of shared resources; second interface means for connecting said peripheral bus to said system bus; a memory location in one of said plurality of shared resources; means for selecting one of said plurality of data processing elements for performing one of said plurality of processing tasks, said selected data processing element including means for generating command codes; lock status circuitry in said one shared resources responsive to a first command code generated by said selected data processing element for returning to said selected data processing element a status code stored in said memory location, said status code indicating to said selected processing element the busy and idle status of each of said plurality of shared system resources; and lock update circuitry in said one shared resource responsive to a second command code generated by said selected data processing element for storing in said memory location an identifying code identifying one of said plurality of shared system resources which said selected data processing element can use for a subsequent data processing task, said identifying code being calculated in a predetermined manner from said command code and a status code stored in said memory location indicating the busy and idle status of each of said plurality of shared system resources.
Claim 3
Dependent Claim
24 words
A computer system according to claim 1 wherein said memory location comprises one location of a plurality of memory locations in a read-only memory.
Claim 4
Dependent Claim
26 words
A computer system according to claim 2 wherein said lock update circuitry operates so that usage of said plurality of shared resources is equal in time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |