Modified interface for parallel access EPROM

Claim 2

Output interface circuitry utilizable for controlling the data output of an electrically programmable read only memory (EPROM) device, the data output of the EPROM device being responsive to transitions in the logic state of an externally-provided output enable signal, the output interface circuitry comprising: (a) a first data transfer circuit for transferring a data input signal to the data output of the EPROM device when the output enable signal is in an active logic state and the data input signal is logic high; (b) a second data transfer circuit for transferring the data input signal to the data output of the EPROM device when the output enable signal is in an active logic state and the data input signal is logic low; (c) data float switching means connected to the first and second data transfer circuits and responsive to a switching signal for forcing the data output of the EPROM device to a high impedance state within a specified data float time t DF after the output enable signal transitions from the active logic state to an inactive logic state; and (d) data hold means responsive to the transition of the output enable signal from the active logic state to the inactive logic state for providing the switching signal to the data float switching means a specified data hold time t DH after the transition of the output enable signal.

Claim 3

Output interface circuity as in claim 1 wherein the active logic state of the output enable signal is a logic low state.

Claim 4

Output interface circuitry utilizable for controlling the data output of an electrically programmable read only memory (EPROM) device, the data output of the EPROM device being responsive to transitions int he logic state of an externally-provided output enable signal, the output interface circuitry comprising: (a) a logic high data path that includes (i) a p-channel pull-up transistor having its source connected to a positive supply and its drain connected to the data output of the EPROM device, and (ii) a NAND gate connected to receive a signal having a logic state that is the compliment of the logic state of the output enable signal and a data input signal as inputs, the output of the NAND gate connected to the gate of the p-channel pull-up transistor via a high data path resistor whereby the logic high data path transfers the data input signal to the data output of the EPROM device when the output enable signal is in a logic low state and the data input signal is in a logic high state; (b) a logic low data path that includes (i) an n-channel pull-down transistor having its source connected to ground and its drain connected to the data output of the EPROM device; and (ii) a NOR gate connected to receive the output enable signal and the data input signal as inputs, the output of the NOR gate connected to the gate of the n-channel pull-down transistor via a low data path resistor whereby the logic low data path transfers the data input signal to the data output of the EPROM device when the output enable signal is in a logic low state and the date input signal is in a logic low state; (c) data hold means responsive to transition of the output enable signal from the logic low state to a logic high state for providing a logic low switching signal and a logic high switching signal a specified data hold time t DH after the transition of the output enable signal; (d) a p-channel feedback transistor having its source connected to the positive supply, its drain connected to the gate of the p-channel pull-up tansistor, and its gate connected to receive the logic low switching signal; and (e) a n-channel feedback transistor having its source connected to ground, its drain connected to the gate of the n-channel pull-down transistor, and its gate connected to receive the logic high switching signal; whereby the data output of the EPROM device is forced to a high impedance state within a specified data float time t DF after the transition of the output enable signal.

Claim 5

Output interface circuitry utilizable for controlling the data output of an electrically programmable read only memory (EPROM) device, the data output of the EPROM device being responsive to transitions int he logic state of an externally-provided output enable signal, the output interface circuitry comprising: (a) a logic high data path that includes (i) a p-channel pull-up transistor having its source connected to a positive supply and its drain connected to the data output of the EPROM device, and (ii) a NAND gate connected to receive a signal having a logic state that is the compliment of the logic state of the output enable signal and a data input signal as inputs, the output of the NAND gate connected to the gate of the p-channel pull-up transistor via a high data path resistor whereby the logic high data path transfers the data input signal to the data output of the EPROM device when the output enable signal is in a logic low state and the data input signal is in a logic high state; (b) a logic low data path that includes (i) an n-channel pull-down transistor having its source connected to ground and its drain connected to the data output of the EPROM device; and (ii) a NOR gate connected to receive the output enable signal and the data input signal as inputs, the output of the NOR gate connected to the gate of the n-channel pull-down transistor via a low data path resistor whereby the logic low data path transfers the data input signal to the data output of the EPROM device when the output enable signal is in a logic low state and the date input signal is in a logic low state; (c) data hold means responsive to transition of the output enable signal from the logic low state to a logic high state for providing a logic low switching signal and a logic high switching signal a specified data hold time t DH after the transition of the output enable signal; (d) a p-channel feedback transistor having its source connected to the positive supply, its drain connected to the gate of the p-channel pull-up tansistor, and its gate connected to receive the logic low switching signal; and (e) a n-channel feedback transistor having its source connected to ground, its drain connected to the gate of the n-channel pull-down transistor, and its gate connected to receive the logic high switching signal; whereby the data output of the EPROM device is forced to a high impedance state within a specified data float time t DF after the transition of the output enable signal.

Claim 6

Output interface circuitry as in claim 3 wherein the data hold means comprises: (a) an invertor; (b) a p-channel input transistor having its source connected to the positive supply, and its drain connected to the input of the invertor and its gate connected to receive the output enable signal; (c) an n-channel input transistor having its source connected to ground, its drain connected to the input of the invertor via a data hold resistor, and its gate connected to receive the output enable signal; and (d) a data hold capacitor connected between the input of the invertor and ground whereby the input to the invertor serves as the logic low switching signal and the output of the invertor serves as the logic high switching signal.