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US5367545A
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Asynchronous signal extracting circuit
Assignee: Fujitsu Ltd
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Filing: 1991-07-04
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Granted: 1994-11-22
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Expires: 2011-07-04
Abstract
Abstract An asynchronous signal extracting circuit for extracting asynchronous signals multiplexed in a synchronization frame, including a demultiplexer unit that demultiplexes asynchronous signals and clock signals which are in synchronism with valid data in the asynchronous signals, a buffer memory that writes valid data in the demultiplexed asynchronous signals using the clock signals as write clock signals, a phase-locked loop circuit that forms read clock signals for the memory, and a control unit that switches the frequency band of a low-pass filter in the circuit periodically or in response to a detection signal of pointer adjustment. The circuit suppresses low-frequency jitter contained in the read clock signals.
Inventors
- 👤 Haruo Yamashita
- 👤 Yuji Takizawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:46
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/05; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/07; H04J3/076; H04L5/00; H04L5/22; H04L5/24
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
116 words
An asynchronous signal extracting circuit comprising: a demultiplexer which demultiplexes asynchronous signals including valid data, detects a pointer adjustment, generates a pointer adjustment detection signal upon detection of the pointer adjustment, and extracts clock signals in synchronism with the demultiplexing of said valid data; a buffer memory that writes said demultiplexed valid data using said clock signals extracted from the asynchronous signals and transmitted from said demultiplexer to said buffer memory as write clock signals; a phase-locked loop circuit which forms read clock signals for said buffer memory; and a control unit which switches a frequency band of a low-pass filter in the phase-locked loop circuit periodically or in response to said pointer adjustment detection signal.
Claim 2
Dependent Claim
116 words
An asynchronous signal extracting circuit comprising: a demultiplexer which demultiplexes asynchronous signals including valid data, detects a pointer adjustment, generates a pointer adjustment detection signal upon detection of the pointer adjustment, and extracts clock signals in synchronism with the demultiplexing of said valid data; a buffer memory that writes said demultiplexed valid data using said clock signals extracted from the asynchronous signals and transmitted from said demultiplexer to said buffer memory as write clock signals; a phase-locked loop circuit which forms read clock signals for said buffer memory; and a control unit which switches a frequency band of a low-pass filter in the phase-locked loop circuit periodically or in response to said pointer adjustment detection signal.
Claim 3
Dependent Claim
29 words
An asynchronous signal extracting circuit according to claim 1, wherein said control unit continuously or in steps switches the frequency band of said low-pass filter within a predetermined period.
Claim 4
Dependent Claim
74 words
An asynchronous signal extracting circuit according to claim 1, wherein said control unit gradually narrows the frequency band of said low-pass filter every time said pointer adjustment detection signal is obtained within a predetermined period of time in said demultiplexer, and returns the frequency band of said low-pass filter to the initial frequency band gradually or at one time when said pointer adjustment detection signal is not obtained within the predetermined period of time.
Claim 5
Dependent Claim
80 words
An asynchronous signal extracting circuit according to claim 1, wherein said phase-locked loop circuit has a counter which counts a phase difference between the write clock signal and the read clock signal of said buffer memory, and a frequency divider of which the frequency-dividing ratio is controlled when the counted content of said counter has reached a setpoint value and produces a frequency-divided output signal as said read clock signal, and wherein said control unit controls said low pass filter.
Claim 6
Dependent Claim
110 words
An asynchronous signal extracting circuit according to claim 1, wherein said buffer memory and said phase-locked loop circuit further comprise two stages, clock signals being outputted from the phase-locked loop circuit of the first stage as read clock signals to the buffer memory of the first stage and as write clock signals to the buffer memory of the second stage, the read clock signals for the buffer memory of the second stage are formed by the phase-locked loop circuit of the second stage, and wherein said control unit controls the frequency band of low-pass filter in the phase-locked loop circuit of at least one of the first and second stage.
Claim 7
Dependent Claim
33 words
An asynchronous signal extracting circuit according to claim 5, wherein said control unit complementarily switches the frequency bands of low-pass filters in phase-locked loop circuit of said first stage and said second stage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |