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US5367491A
Expired / Lapsed
US
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Apparatus for automatically initiating a stress mode of a semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-01-27
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Granted: 1994-11-22
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Expires: 2012-01-27
Abstract
Abstract In a highly integrated semiconductor memory device, apparatus for setting a stress mode without applying a stress voltage from the exterior is provided. A triggered time point T S to a stress mode can be set by greatly raising an internal supply voltage when the external supply voltage is raised to a voltage over the stress voltage.
Inventors
- 👤 Jin-Man Han
- 👤 Jong-Hoon Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:06
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46; G11C29/50; G01R31/30; G06; G06F; G06F2201/00; G06F2201/81
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
104 words
A circuit for initiating a stress mode of a semiconductor memory device using an external supply voltage and an internal supply voltage, comprising: a differential amplifier connected to receive said external supply voltage and said internal supply voltage; a level trigger circuit connected to receive an output of said differential amplifier; a bias circuit connected to receive an output of said level trigger circuit; and a driving insulation gate field effect transistor receiving an output of said bias circuit through a gate thereof, said driving insulation gate field effect transistor having a channel connected between said external supply voltage and said internal supply voltage.
Claim 2
Dependent Claim
104 words
A circuit for initiating a stress mode of a semiconductor memory device using an external supply voltage and an internal supply voltage, comprising: a differential amplifier connected to receive said external supply voltage and said internal supply voltage; a level trigger circuit connected to receive an output of said differential amplifier; a bias circuit connected to receive an output of said level trigger circuit; and a driving insulation gate field effect transistor receiving an output of said bias circuit through a gate thereof, said driving insulation gate field effect transistor having a channel connected between said external supply voltage and said internal supply voltage.
Claim 3
Dependent Claim
78 words
The circuit as claimed in claim 1, wherein said level trigger circuit is comprised of: an insulation gate field effect transistor having a gate connected to an output terminal of said differential amplifier, and having a channel, one terminal of said channel being connected to said external supply voltage; and a trigger node connected to a second terminal of said channel of said insulation gate field effect transistor and coupled to an input terminal of said bias circuit.
Claim 4
Dependent Claim
195 words
A circuit for initiating a stress mode of a semiconductor memory device using an external supply voltage and an internal supply voltage, comprising: a first voltage node having a first potential dependent upon said internal supply voltage; a second voltage node having a second potential dependent upon said external supply voltage; a differential amplifier connected to receive said first and second potentials of said first and second voltage nodes, and having an output node; a first insulation gate field effect transistor having a gate connected to said output node of said differential amplifier; a charging node connected to one terminal of a channel of said first insulation gate field effect transistor, and having a third potential dependent upon said external supply voltage; a trigger node connected to a second terminal of said channel of said first insulation gate field effect transistor; a bias circuit having an input terminal connected to said trigger node; and, a second insulation gate field effect transistor connected to receive an output of said bias circuit through a gate thereof, said second insulation gate field effect transistor having a channel connected between said external supply voltage and said internal supply voltage.
Claim 5
Dependent Claim
195 words
A circuit for initiating a stress mode of a semiconductor memory device using an external supply voltage and an internal supply voltage, comprising: a first voltage node having a first potential dependent upon said internal supply voltage; a second voltage node having a second potential dependent upon said external supply voltage; a differential amplifier connected to receive said first and second potentials of said first and second voltage nodes, and having an output node; a first insulation gate field effect transistor having a gate connected to said output node of said differential amplifier; a charging node connected to one terminal of a channel of said first insulation gate field effect transistor, and having a third potential dependent upon said external supply voltage; a trigger node connected to a second terminal of said channel of said first insulation gate field effect transistor; a bias circuit having an input terminal connected to said trigger node; and, a second insulation gate field effect transistor connected to receive an output of said bias circuit through a gate thereof, said second insulation gate field effect transistor having a channel connected between said external supply voltage and said internal supply voltage.
Claim 6
Dependent Claim
32 words
The circuit as claimed in claim 3, wherein said first potential is connected to an output of a first voltage division means connected between said internal supply voltage and a ground voltage.
Claim 7
Dependent Claim
32 words
The circuit as claimed in claim 3, wherein said second potential is connected to an output of a second voltage division means connected between said external supply voltage and a ground voltage.
Claim 8
Dependent Claim
195 words
A circuit for initiating a stress mode of a semiconductor memory device using an external supply voltage and an internal supply voltage, comprising: a first voltage node having a first potential dependent upon said internal supply voltage; a second voltage node having a second potential dependent upon said external supply voltage; a differential amplifier connected to receive said first and second potentials of said first and second voltage nodes, and having an output node; a first insulation gate field effect transistor having a gate connected to said output node of said differential amplifier; a charging node connected to one terminal of a channel of said first insulation gate field effect transistor, and having a third potential dependent upon said external supply voltage; a trigger node connected to a second terminal of said channel of said first insulation gate field effect transistor; a bias circuit having an input terminal connected to said trigger node; and, a second insulation gate field effect transistor connected to receive an output of said bias circuit through a gate thereof, said second insulation gate field effect transistor having a channel connected between said external supply voltage and said internal supply voltage.
Claim 9
Dependent Claim
195 words
A circuit for initiating a stress mode of a semiconductor memory device using an external supply voltage and an internal supply voltage, comprising: a first voltage node having a first potential dependent upon said internal supply voltage; a second voltage node having a second potential dependent upon said external supply voltage; a differential amplifier connected to receive said first and second potentials of said first and second voltage nodes, and having an output node; a first insulation gate field effect transistor having a gate connected to said output node of said differential amplifier; a charging node connected to one terminal of a channel of said first insulation gate field effect transistor, and having a third potential dependent upon said external supply voltage; a trigger node connected to a second terminal of said channel of said first insulation gate field effect transistor; a bias circuit having an input terminal connected to said trigger node; and, a second insulation gate field effect transistor connected to receive an output of said bias circuit through a gate thereof, said second insulation gate field effect transistor having a channel connected between said external supply voltage and said internal supply voltage.
Claim 10
Dependent Claim
32 words
The circuit as claimed in claim 6, wherein said first potential is connected to an output of a first voltage division means connected between said internal supply voltage and a ground voltage.
Claim 11
Dependent Claim
32 words
The circuit as claimed in claim 6, wherein said second potential is connected to an output of a second voltage division means connected between said external supply voltage and a ground voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |