High speed output buffer with reduced voltage bounce and no cross current

Claim 2

An IC output driver device, comprising: an output line; a power supply bus; a ground bus; an input line; a P-channel driver transistor, having its source coupled to the power supply bus and its drain coupled to the output line, for amplifying a logic high output signal, having circuitry coupled to the gate of the P-channel driver transistor for controlling a output current bounce on the output line, including: an output enable signal line; a first NAND gate, having first and second inputs, the first input being coupled to the input line and the second input being coupled to the output enable signal line; first and second inverters, each inverter receiving an input from the first NAND gate; a second NAND gate having first and second inputs, the first input being coupled to the output of the second inverter and the second input being coupled to the input line; a P-channel pull-up transistor, having its gate coupled to the output of the first inverter, its drain coupled to the gate of the P-channel driver transistor, and its source coupled to the power supply bus; a P-channel pull-down transistor having its gate coupled to the output of the first NAND, its source coupled to the drain of the P-channel pull-up transistor and the gate of the P-channel driver transistor, and its drain coupled to the ground bus; and the gate of the P-channel driver transistor coupled to the output of the second NAND gate.

Claim 3

The IC driver device of claim 1, further comprising: an N-channel driver transistor, having its drain coupled to the output line and the drain of the P-channel driver transistor, and its source coupled to the ground bus, for amplifying the output of a logic low signal, having circuitry coupled to the gate of the N-channel driver transistor for controlling current bounce on the output line, including: a complement output enable signal line; a first NOR gate, said first NOR gate having first and second inputs, the first input being coupled to the input line and the second input being coupled to the complement output enable signal line; third and fourth inverters, each having an input coupled to the output of the first NOR gate; a second NOR gate, having first and second inputs, the first input being coupled to the input line and the second input being coupled to the output of said fourth inverter; an N-channel pull-up transistor, having its gate coupled to the output of the first NOR gate, its drain coupled to the power supply bus, and its source coupled to the gate of the N-channel driver transistor; an N-channel pull-down transistor, having its gate coupled to the output of the third inverter, its source coupled to the ground bus, and its drain coupled to the gate of the N-channel driver transistor and to the source of the N-channel pull-up transistor; and said second NOR gate having its output coupled to the gate of the N-channel driver transistor.

Claim 4

A non-inverting output driver circuit comprising: an input node; an output node; a P-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a power supply bus; gate control circuitry for the P-channel driver transistor including; a P-channel insulated-gate, field-effect pull-up transistor having a gate, and a channel which couples the power supply bus to the gate of the P-channel driver transistor; a P-channel insulated-gate, field-effect pull-down transistor having a gate, and a channel which couples the ground bus to the gate of the P-channel driver transistor; a first NAND gate having an output coupled to the P-channel pull-down transistor, a first input for receiving an output enable signal, and a second input coupled to the input node; a first inverter having an input coupled to the output of said first NAND gate, and also having an output coupled to the gate of the P-channel pull-up transistor; a second inverter having an output, and also having an input coupled to the output of said first NAND gate; a second NAND gate having an output coupled to the gate of the P-channel driver transistor, a first input coupled to the output of said second inverter, and a second input coupled to the input node; an N-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a ground bus; gate control circuitry for the N-channel driver transistor including; an N-channel insulated-gate, field-effect pull-up transistor having a gate, and a channel which couples the power supply bus to the gate of the N-channel driver transistor; an N-channel insulated-gate, field-effect pull-down transistor having a gate, and a channel which couples the ground bus to the gate of the N-channel driver transistor; a first NOR gate having an output coupled to the gate of the N-channel pull-up transistor, a first input for receiving a complement of the output enable signal, and a second input coupled to the input node; a third inverter having an input coupled to the output of said first NOR gate, and also having an output coupled to the gate of the N-channel pull-down transistor; a fourth inverter having an input coupled to the output of said first NOR gate, and also having an output; and a second NOR gate having an output coupled to the gate of the N-channel driver transistor, a first input coupled to the output of said fourth inverter, and a second input coupled to the input node.

Claim 5

A non-inverting output driver circuit comprising: an input node; an output node; a P-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a power supply bus; gate control circuitry for the P-channel driver transistor including; a P-channel insulated-gate, field-effect pull-up transistor having a gate, and a channel which couples the power supply bus to the gate of the P-channel driver transistor; a P-channel insulated-gate, field-effect pull-down transistor having a gate, and a channel which couples the ground bus to the gate of the P-channel driver transistor; a first NAND gate having an output coupled to the P-channel pull-down transistor, a first input for receiving an output enable signal, and a second input coupled to the input node; a first inverter having an input coupled to the output of said first NAND gate, and also having an output coupled to the gate of the P-channel pull-up transistor; a second inverter having an output, and also having an input coupled to the output of said first NAND gate; a second NAND gate having an output coupled to the gate of the P-channel driver transistor, a first input coupled to the output of said second inverter, and a second input coupled to the input node; an N-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a ground bus; gate control circuitry for the N-channel driver transistor including; an N-channel insulated-gate, field-effect pull-up transistor having a gate, and a channel which couples the power supply bus to the gate of the N-channel driver transistor; an N-channel insulated-gate, field-effect pull-down transistor having a gate, and a channel which couples the ground bus to the gate of the N-channel driver transistor; a first NOR gate having an output coupled to the gate of the N-channel pull-up transistor, a first input for receiving a complement of the output enable signal, and a second input coupled to the input node; a third inverter having an input coupled to the output of said first NOR gate, and also having an output coupled to the gate of the N-channel pull-down transistor; a fourth inverter having an input coupled to the output of said first NOR gate, and also having an output; and a second NOR gate having an output coupled to the gate of the N-channel driver transistor, a first input coupled to the output of said fourth inverter, and a second input coupled to the input node.

Claim 6

A non-inverting output driver circuit comprising: an input node; an output node; a P-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a power supply bus; gate control circuitry for the P-channel driver transistor including; a P-channel insulated-gate, field-effect pull-up transistor having a gate, and a channel which couples the power supply bus to the gate of the P-channel driver transistor; a P-channel insulated-gate, field-effect pull-down transistor having a gate, and a channel which couples the ground bus to the gate of the P-channel driver transistor; first and second NAND gates, each having first and second inputs and an output; the first input of said first NAND gate coupled to an output enable signal, the second input of said first NAND gate being coupled to the input node, the second input of said second NAND gate being coupled to the input node, the output of said second NAND gate being coupled to the gate of the P-channel driver transistor, the output of said first NAND gate being directly coupled to the P-channel pull-down transistor and indirectly coupled to both the P-channel pull-up transistor and the first input of said second NAND gate through an inverter; an N-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a ground bus; gate control circuitry for the N-channel driver transistor including; an N-channel insulated-gate, field-effect pull-up transistor having a gate, and a channel which couples the power supply bus to the gate of the N-channel driver transistor; an N-channel insulated-gate, field-effect pull-down transistor having a gate, and a channel which couples the ground bus to the gate of the N-channel driver transistor; first and second NOR gates, each having first and second inputs and an output; the first input of said first NOR gate coupled to a complement of the output enable signal, the second input of said first NOR gate being coupled to the input node, the second input of said second NOR gate being coupled to the input node, the output of said second NOR gate being coupled to the gate of the P-channel driver transistor, the output of said first NOR gate being directly coupled to the N-channel pull-up transistor and indirectly coupled to both the N-channel pull-down transistor and the first input of said second NOR gate through an inverter.

Claim 7

A non-inverting output driver circuit comprising: an input node; an output node; a P-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a power supply bus; gate control circuitry for the P-channel driver transistor including; a P-channel insulated-gate, field-effect pull-up transistor having a gate, and a channel which couples the power supply bus to the gate of the P-channel driver transistor; a P-channel insulated-gate, field-effect pull-down transistor having a gate, and a channel which couples the ground bus to the gate of the P-channel driver transistor; first and second NAND gates, each having first and second inputs and an output; the first input of said first NAND gate coupled to an output enable signal, the second input of said first NAND gate being coupled to the input node, the second input of said second NAND gate being coupled to the input node, the output of said second NAND gate being coupled to the gate of the P-channel driver transistor, the output of said first NAND gate being directly coupled to the P-channel pull-down transistor and indirectly coupled to both the P-channel pull-up transistor and the first input of said second NAND gate through an inverter; an N-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a ground bus; gate control circuitry for the N-channel driver transistor including; an N-channel insulated-gate, field-effect pull-up transistor having a gate, and a channel which couples the power supply bus to the gate of the N-channel driver transistor; an N-channel insulated-gate, field-effect pull-down transistor having a gate, and a channel which couples the ground bus to the gate of the N-channel driver transistor; first and second NOR gates, each having first and second inputs and an output; the first input of said first NOR gate coupled to a complement of the output enable signal, the second input of said first NOR gate being coupled to the input node, the second input of said second NOR gate being coupled to the input node, the output of said second NOR gate being coupled to the gate of the P-channel driver transistor, the output of said first NOR gate being directly coupled to the N-channel pull-up transistor and indirectly coupled to both the N-channel pull-down transistor and the first input of said second NOR gate through an inverter.

Claim 8

A non-inverting output driver circuit comprising: an input node; an output node; a P-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a power supply bus, said P-channel driver transistor having control circuitry coupled to its gate; an N-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a ground bus, said N-channel driver transistor having control circuitry coupled to its gate; the gate control circuitry for said P-channel driver transistor operative to deactivate said P-channel driver transistor before said N-channel driver transistor is activated by its gate control circuitry, the gate control circuitry for said P-channel driver transistor comprising: a NAND gate having an output coupled to the gate of said P-channel driver transistor, a first input coupled to said input node via a first path, a second input coupled to said input node via a second path, said first path being electrically shorter than said second path; a P-channel pull-up transistor having a gate coupled to said input node via a fifth path, and a channel which couples the power supply bus to the gate of said P-channel driver transistor; a P-channel pull-down transistor having a gate coupled to said input node via a sixth path, and a channel which couples the ground bus to the gate of said P-channel driver transistor, said sixth path being electrically shorter than said fifth path; and the gate control circuitry for said N-channel driver transistor operative to deactivate said N-channel driver transistor before said P-channel driver transistor is activated by its gate control circuitry, the gate control circuitry for said N-channel driver transistor comprising: a NOR gate having an output coupled to the gate of said N-channel driver transistor, a first input coupled to said input node via a third path, and a second input coupled to said input node via a fourth path, said third path being electrically shorter than said fourth path; an N-channel pull-up transistor having a gate coupled to said input node via a seventh path, and a channel which couples the power supply bus to the gate of said N-channel driver transistor; an N-channel pull-down transistor having a gate coupled to said input node via an eighth path, and a channel which couples the ground bus to the gate of said N-channel driver transistor, said seventh path being electrically shorter than said eighth path.

Claim 9

A non-inverting output driver circuit comprising: an input node; an output node; a P-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a power supply bus, said P-channel driver transistor having control circuitry coupled to its gate; an N-channel insulated-gate, field-effect driver transistor having a gate, and a channel which couples the output node to a ground bus, said N-channel driver transistor having control circuitry coupled to its gate; the gate control circuitry for said P-channel driver transistor operative to deactivate said P-channel driver transistor before said N-channel driver transistor is activated by its gate control circuitry, the gate control circuitry for said P-channel driver transistor comprising: a NAND gate having an output coupled to the gate of said P-channel driver transistor, a first input coupled to said input node via a first path, a second input coupled to said input node via a second path, said first path being electrically shorter than said second path; a P-channel pull-up transistor having a gate coupled to said input node via a fifth path, and a channel which couples the power supply bus to the gate of said P-channel driver transistor; a P-channel pull-down transistor having a gate coupled to said input node via a sixth path, and a channel which couples the ground bus to the gate of said P-channel driver transistor, said sixth path being electrically shorter than said fifth path; and the gate control circuitry for said N-channel driver transistor operative to deactivate said N-channel driver transistor before said P-channel driver transistor is activated by its gate control circuitry, the gate control circuitry for said N-channel driver transistor comprising: a NOR gate having an output coupled to the gate of said N-channel driver transistor, a first input coupled to said input node via a third path, and a second input coupled to said input node via a fourth path, said third path being electrically shorter than said fourth path; an N-channel pull-up transistor having a gate coupled to said input node via a seventh path, and a channel which couples the power supply bus to the gate of said N-channel driver transistor; an N-channel pull-down transistor having a gate coupled to said input node via an eighth path, and a channel which couples the ground bus to the gate of said N-channel driver transistor, said seventh path being electrically shorter than said eighth path.

Claim 10

The non-inverting output driver circuit of claim 5, wherein said second and fourth paths each contain at least two more gate delays than said first and third paths, respectively.

Claim 11

The non-inverting output driver circuit of claim 6, wherein an inverter is utilized to provide an additional gate delay in each of said second and fourth paths.

Claim 12

The non-inverting output driver circuit of claim 5, wherein said fifth and eighth paths each contain at least one more gate delay than said sixth and seventh paths, respectively.

Claim 13

The non-inverting output driver circuit of claim 8, wherein inverters are utilized to provide a gate delays.