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US5365528A
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Method for testing delay faults in non-scan sequential circuits
Assignee: Nokia Bell Labs
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Filing: 1992-04-03
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Granted: 1994-11-15
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Expires: 2012-04-03
Abstract
Abstract To detect a delay fault along a signal path of interest (12) in a sequential digital circuit (10), a source flip-flop (14) and a destination flip-flop (16), proximate the beginning and end of the path, respectively, are designated in the circuit. Next, the signal path is activated to establish what logic values are necessary at the input of each of a set of combinational elements (181-18p) in the path to propagate a selected signal transition from the source flip-flop to the destination flip-flop. A first and second backward justification process is carried out to synthesize a first sequence to propagate a selected logic value from a primary circuit input to the source flip-flop to cause it to generate the selected signal transition to propagate to the destination flip-flop. A second backward justification process is carried out to synthesize a second vector sequence which serves to propagate the value latched in the destination flip-flop to a primary output. The vectors of the first and second sequences are then applied at periodic intervals using a slow clock, except that the rated clock is applied to the last vector of the first sequence to propagate the logic value affected by the delay fault ultimately to the primary output. By comparing the value propagated to the primary output to the expected correct logic value, a determination can be made as to the existence of a delay fault.
Inventors
- 👤 Vishwani D. Agrawal
- 👤 Tapan J. Chakraborty
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:20
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318328
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
371 words
A method for detecting whether a signal transition has propagated within a prescribed interval along a signal path of interest in a digital circuit having at least one primary input and at least one primary output, and including a plurality of flip-flops, comprising the steps of: designating a first (source) flip-flop in the digital circuit which is proximate to a first end of the signal path of interest and a second (destination) flip-flop which is proximate a second end of the signal path of interest; activating the signal path to establish what logic value is necessary at each of a plurality of intermediate portions of the signal path in order for a selected signal transition to propagate from the source flip-flop to the destination flip-flop performing a first backward justification, in accordance with the activation of the signal path, to synthesize a first sequence of vectors which, when applied to the primary input, serves to propagate a selected logic value from the primary input to the source flip-flop to cause the source flip-flop to generate the selected logic transition and to propagate the signal transition to the destination flip-flop so that a logic value is latched therein; performing a second backward justification, in accordance with the activation of the signal path, to synthesize a second sequence of vectors, which, when applied to the primary input, serves to propagate the logic value that has been latched into the destination flip-flop to the primary output; periodically applying a successive one of the vectors of the first sequence to the primary input such that the selected logic value is propagated from the primary input to the source flip-flop, and that the selected signal transition is generated by the source flip-flop and propagates therefrom to the destination flip-flop within the predetermined interval in the absence of a delay fault; periodically applying a successive one of the vectors of the second sequence to the primary input to cause the destination flip-flop to propagate the logic value that has been latched therein following application of the first sequence of vectors to the primary output; and comparing the logic value propagated to the primary output to the preselected logic value to determine if a delay fault is present.
Claim 2
Independent Claim
371 words
A method for detecting whether a signal transition has propagated within a prescribed interval along a signal path of interest in a digital circuit having at least one primary input and at least one primary output, and including a plurality of flip-flops, comprising the steps of: designating a first (source) flip-flop in the digital circuit which is proximate to a first end of the signal path of interest and a second (destination) flip-flop which is proximate a second end of the signal path of interest; activating the signal path to establish what logic value is necessary at each of a plurality of intermediate portions of the signal path in order for a selected signal transition to propagate from the source flip-flop to the destination flip-flop performing a first backward justification, in accordance with the activation of the signal path, to synthesize a first sequence of vectors which, when applied to the primary input, serves to propagate a selected logic value from the primary input to the source flip-flop to cause the source flip-flop to generate the selected logic transition and to propagate the signal transition to the destination flip-flop so that a logic value is latched therein; performing a second backward justification, in accordance with the activation of the signal path, to synthesize a second sequence of vectors, which, when applied to the primary input, serves to propagate the logic value that has been latched into the destination flip-flop to the primary output; periodically applying a successive one of the vectors of the first sequence to the primary input such that the selected logic value is propagated from the primary input to the source flip-flop, and that the selected signal transition is generated by the source flip-flop and propagates therefrom to the destination flip-flop within the predetermined interval in the absence of a delay fault; periodically applying a successive one of the vectors of the second sequence to the primary input to cause the destination flip-flop to propagate the logic value that has been latched therein following application of the first sequence of vectors to the primary output; and comparing the logic value propagated to the primary output to the preselected logic value to determine if a delay fault is present.
Claim 3
Dependent Claim
61 words
The method according to claim 1 wherein the vectors of the first sequence are applied to the primary inputs at different speeds so that the speed at which the selected logic value propagates from the primary input to the source flip-flop is slower than the speed at which the selected signal transition propagates from the source flip-flop to the destination flip-flop.
Claim 4
Dependent Claim
60 words
The method according to claim 2 wherein the vectors of the second sequence are applied to the primary input at such a speed that the propagation of the logic value which has been latched in the destination flip-flop to the primary output is slower than the propagation of the selected signal transition from the source flip-flop to the destination flip-flop.
Claim 5
Dependent Claim
48 words
The method according to claim 1 including the steps of: checking whether any conflicts arise during the first backward justification process; and if so re-executing the first backward justification process to eliminate all conflicts if possible; otherwise declaring an untestable fault condition when conflict elimination is not possible.
Claim 6
Dependent Claim
62 words
The method according to claim 4 further including the steps of: checking whether any conflicts arise during the second backward justification process; and if so re-executing the second backward justification process to eliminate all conflicts if possible; otherwise re-executing the first backward justification process to eliminate all conflicts if possible; otherwise declaring an untestable fault condition when conflict elimination is not possible.
Claim 7
Dependent Claim
25 words
The method according to claim 1 wherein only the source flip-flop and destination flip-flops are affected by a delay along the signal path of interest.
Claim 8
Dependent Claim
58 words
The method according to claim 1 wherein each flip-flop in the circuit (excepting the one designated as the destination flip-flop and those maintaining steady state values without hazard during transition propagation through the path of interest) has a don't care value latched therein immediately after propagation of the selected signal transition from the source to the destination flip-flop.
Claim 9
Dependent Claim
64 words
The method according to claim 1 wherein each flip-flop in the circuit that must assume a signal value immediately after propagation of the selected signal transition from the source flip-flop to the destination flip-flop in order to propagate the state of the destination flip-flop to a primary output, must maintain that signal value without hazard during the last two vectors of the first sequence.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-14 | 1998-05-16 | 1998-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-14 | 2002-05-16 | 2002-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-14 | 2006-05-16 | 2006-11-15 | $7700.00 | Window Closed / Lapsed |