Logical comparison circuit

Claim 2

A logical comparison circuit comprising: an interleave circuit including n latch circuits, whereby a sample data signal is latched in said n latch circuits in synchronization with a test clock, n being an integer equal to or greater than 2, for conversion to n trains of low-speed signals each having a period n times longer than that of said test clock; a multi-phase pulse generator for generating n pulse signals having different phases synchronized with an expected value pattern signal; a period converter, operatively connected to said interleave circuit and said multi-phase pulse generator, for converting said converted low-speed signals from said interleave circuit which are extracted by said n pulse signals having different phases, into a high-speed signal; and a comparator, operatively connected to said period converter, for comparing said high-speed signals with said expected value pattern signal to decide whether said sample data signal coincides with said expected value pattern signal.

Claim 3

A logical comparator according to claim 1, wherein said multi-phase pulse generator includes counter means which counts first system clock pulses and generates n trains of pulse signals each having a period n times longer than that of said first system clock pulses and sequentially delayed in phase by a 1/n period, and wherein said period converter includes n AND gates which are supplied at one input with said n trains of pulse signals as gate signals, respectively, and at the other input with the outputs from said n latch circuits and an OR gate for combining the outputs of said AND gates into said high-speed signal.

Claim 4

The logical comparison circuit of claim 2, wherein said interleave circuit includes: second counter means for counting pluses of said test clock and generating n trains of second gate signals each having a period n times longer than that of said test clock pulses and sequentially delayed in phase by a 1/n period; and n second AND gates supplied at one input with said n trains of second gate signals, respectively, for permitting the passage therethrough of said test clock pulses supplied to the other inputs thereof, the output of said n second AND gates being applied to said n latch circuits.

Claim 5

A logical comparison circuit according to claim 3, further comprising: n cascade-connected latches which fetch therein said expected value pattern signal in synchronization with a second system clock pulse and shift said expected value pattern signal from one stage to another upon each occurrence of said second system clock pulse, said expected value pattern signal from the last one of said n latches being applied to said comparator; and branch condition detector means for outputting a detected signal when detecting that said sample data signal has reached a predetermined branch condition value, said branch condition detector means including: n comparators for comparing said expected value pattern signal input into said n latches and said n trains of low-speed signals from said n latch circuits of said interleave circuit, respectively; n comparison result strobe-out means for strobing out former one-third portions of the cycles of the outputs from said n comparators; and combining means for combining the outputs of said n comparison result strobe-out means into an output signal.

Claim 6

A logical comparison circuit according to claim 4, wherein said n comparison result strobe-out means includes n third AND gates controlled by said n trains of second gate signals from said second counter means to strobe out the results of the comparison by said n comparators.