Data reading circuit having a clamping circuit for clamping a pair of data buses to predetermined potentials

Claim 2

A data reading circuit comprising: a pair of data buses supplied with complementary potential respectively; a first reference voltage source having a first potential; a second reference voltage source having a second potential; a first switch connected to said first reference voltage source and said pair of data buses and responsive to a first clamping signal to electrically connect said first reference voltage source to said pair of data buses; and a second switch connected to said second reference voltage source and said pair of data buses and responsive to a second clamping signal to electrically connect said second reference voltage source to said pair of data buses.

Claim 3

A data reading circuit according to claim 1, wherein said first switch comprises: a first control terminal supplied with a first control signal; a first transistor having a control electrode connected to said first control terminal, a first electrode connected to said first reference voltage source and a second electrode connected to one of said pair of data buses; and a second transistor having a control electrode connected to said first control terminal, a third electrode connected to said first reference voltage source and a fourth electrode connected to the other of said pair of data buses.

Claim 4

A data reading circuit according to claim 1, wherein said second switch comprises: a second control terminal supplied with a second control signal; a third transistor having a control electrode connected to said second control terminal, a fifth electrode connected to said second reference voltage source and a sixth electrode connected to one of said pair of data buses; and a fourth transistor having a control electrode connected to said second control terminal, a seventh electrode connected to said second reference voltage source and an eighth electrode connected to the other of said pair of data buses.

Claim 5

A data reading circuit according to claim 1 wherein said first potential is a power source potential.

Claim 6

A data reading circuit according to claim 4, wherein the second potential is a ground potential.

Claim 7

A data reading circuit according to claim 1, wherein said second potential is a ground potential.

Claim 8

A data reading circuit, comprising: a plurality of word lines; a pair of complementary bit lines intersecting said plurality of word lines; a pair of complementary data buses corresponding to said pair of bit lines; a plurality of memory cells respectively provided at positions where said pairs of word lines and said pair of complementary bit lines intersect respectively, said memory cells having predetermined data stored therein; a column switch connected between said pair of bit lines and said pair of data buses and having a column signal input terminal supplied with a column signal, said column switch being responsive to activation of the column signal to electrically connect said pair of bit lines to said pair of data buses; a first reference voltage source having a first potential; a second reference voltage source having a second potential; an equalizing circuit connected to said first reference voltage source and said pair of data buses and having an equalize signal input terminal supplied with an equalize signal, said equalizing circuit being responsive to activation of the equalize signal to electrically connect said first reference voltage source and said pair of data buses and to electrically connect one of said pair of data buses to the other thereof; and a clamping circuit for alternatively clamping the first potential or the second potential on each of said pair of data buses., said clamping circuit connected to said first reference voltage source, said second reference voltage source and said pair of data buses and having a first clamping signal input terminal supplied with a first clamping signal and a second clamping signal input terminal supplied with a second clamping signal, said clamping circuit being responsive to activation of the first clamping signal to electrically connect said first reference voltage source to said pair of data buses and responsive to activation of the second clamping signal to electrically connect said second reference voltage source to said pair of data buses.

Claim 9

A data reading circuit, comprising: a plurality of word lines; a pair of complementary bit lines intersecting said plurality of word lines; a pair of complementary data buses corresponding to said pair of bit lines; a plurality of memory cells respectively provided at positions where said pairs of word lines and said pair of complementary bit lines intersect respectively, said memory cells having predetermined data stored therein; a column switch connected between said pair of bit lines and said pair of data buses and having a column signal input terminal supplied with a column signal, said column switch being responsive to activation of the column signal to electrically connect said pair of bit lines to said pair of data buses; a first reference voltage source having a first potential; a second reference voltage source having a second potential; an equalizing circuit connected to said first reference voltage source and said pair of data buses and having an equalize signal input terminal supplied with an equalize signal, said equalizing circuit being responsive to activation of the equalize signal to electrically connect said first reference voltage source and said pair of data buses and to electrically connect one of said pair of data buses to the other thereof; and a clamping circuit for alternatively clamping the first potential or the second potential on each of said pair of data buses., said clamping circuit connected to said first reference voltage source, said second reference voltage source and said pair of data buses and having a first clamping signal input terminal supplied with a first clamping signal and a second clamping signal input terminal supplied with a second clamping signal, said clamping circuit being responsive to activation of the first clamping signal to electrically connect said first reference voltage source to said pair of data buses and responsive to activation of the second clamping signal to electrically connect said second reference voltage source to said pair of data buses.

Claim 10

A data reading circuit according to claim 7, wherein said first potential is a power source potential.

Claim 11

A data reading circuit according to claim 8, wherein the second potential is a ground potential.

Claim 12

A data reading circuit according to claim 7, wherein said clamping circuit comprises: a first node connected to one of said pair of data buses; a second node connected to the other of said pair of data buses; a first switch connected to said first clamping signal input terminal, said first reference voltage source and said first node and responsive to said first clamping signal to electrically connect said first reference voltage source to said first node; a second switch connected to said first clamping signal input terminal, said first reference voltage source and said second node and responsive to said first clamping signal to electrically connect said first reference voltage source to said second node; a third switch connected to said second clamping signal input terminal, said second reference voltage source and said first node and responsive to said second clamping signal to electrically connect said second reference voltage source to said first node; and a fourth switch connected to said second clamping signal input terminal, said second reference voltage source and said second node and responsive to said second clamping signal to electrically connect said second reference voltage source to said second node.

Claim 13

A data reading circuit according to claim 10, wherein said first through fourth switches are MOS transistors.

Claim 14

A data reading circuit according to claim 11, wherein said first through fourth switches are N-type MOS transistors.

Claim 15

A data reading circuit according to claim 7, wherein during a first time period, an activated signal is supplied to said equalize signal input terminal and said first and second clamping signal input terminals and a non-activated signal is supplied to said column signal input terminal, and during a second time period subsequent to said first period, an activated signal is supplied to said column signal input terminal and said first clamping signal input terminal and a non-activated signal is supplied to said equalize signal input terminal and said second clamping signal input terminal.

Claim 16

A data reading circuit according to claim 7, wherein said second potential is a ground potential.

Claim 17

A data reading circuit comprising: a pair of data lines supplied with complementary potential levels respectively; a first reference voltage source having a first potential; a second reference voltage source having a second potential; a first clamping signal input terminal supplied with a first clamping signal; a second clamping signal input terminal supplied with a second clamping signal; a first node connected to one of said pair of data lines; a second node connected to the other of said pair of data lines; a first switch connected to said first clamping signal input terminal, said first reference voltage source and said first node and responsive to said first clamping signal to electrically connect said first reference voltage source to said first node; a second switch connected to said first clamping signal input terminal, said first reference voltage source and said second node and responsive to said first clamping signal to electrically connect said first reference voltage source to said second node; a third switch connected to said second clamping signal input terminal, said second reference voltage source and said first node and responsive to said second clamping signal to electrically connect said second reference voltage source to said first node; and a fourth switch connected to said second clamping signal input terminal, said second reference voltage source and said second node and responsive to said second clamping signal to electrically connect said second reference voltage source to said second node.

Claim 18

A data reading circuit comprising: a pair of data lines supplied with complementary potential levels respectively; a first reference voltage source having a first potential; a second reference voltage source having a second potential; a first clamping signal input terminal supplied with a first clamping signal; a second clamping signal input terminal supplied with a second clamping signal; a first node connected to one of said pair of data lines; a second node connected to the other of said pair of data lines; a first switch connected to said first clamping signal input terminal, said first reference voltage source and said first node and responsive to said first clamping signal to electrically connect said first reference voltage source to said first node; a second switch connected to said first clamping signal input terminal, said first reference voltage source and said second node and responsive to said first clamping signal to electrically connect said first reference voltage source to said second node; a third switch connected to said second clamping signal input terminal, said second reference voltage source and said first node and responsive to said second clamping signal to electrically connect said second reference voltage source to said first node; and a fourth switch connected to said second clamping signal input terminal, said second reference voltage source and said second node and responsive to said second clamping signal to electrically connect said second reference voltage source to said second node.

Claim 19

A data reading circuit according to claim 15, wherein said first through fourth switches are MOS transistors.

Claim 20

A data reading circuit according to claim 16, wherein said first through fourth switches are N-type MOS transistors.

Claim 21

A data reading circuit according to claim 15, wherein said second potential is a ground potential.

Claim 22

A data reading circuit according to claim 15, wherein said first potential is a power source potential.

Claim 23

A data reading circuit according to claim 19, wherein the second potential is a ground potential.