US5365346A — Image signal processor generating reduced memory …

Claim 1

Independent Claim 142 words

An image signal processor comprising: converting means for demodulating a composite color video signal into color difference signals and for matrixing the difference signals with the composite color video signal so as to cause the color difference signals to be converted into respective primary color signals having carrier color signal components superimposed thereon; a digitizing circuit for digitizing an output from said converting means at a threshold level; a clock pulse generating circuit for generating clock pulses synchronized with a color burst signal included in the composite color video signal and having a frequency n times the frequency of the color burst signal, wherein n represents a positive integer not smaller than 2; and memory means for sampling and storing an output from said digitizing circuit when the clock pulses from said clock pulse generating circuit are applied as sampling clock pulses.

Claim 2

Dependent Claim 142 words

An image signal processor comprising: converting means for demodulating a composite color video signal into color difference signals and for matrixing the difference signals with the composite color video signal so as to cause the color difference signals to be converted into respective primary color signals having carrier color signal components superimposed thereon; a digitizing circuit for digitizing an output from said converting means at a threshold level; a clock pulse generating circuit for generating clock pulses synchronized with a color burst signal included in the composite color video signal and having a frequency n times the frequency of the color burst signal, wherein n represents a positive integer not smaller than 2; and memory means for sampling and storing an output from said digitizing circuit when the clock pulses from said clock pulse generating circuit are applied as sampling clock pulses.

Claim 3

Dependent Claim 117 words

An image signal processor comprising: clock pulse generating means for generating first clock pulses and also for generating second clock pulses synchronized with the first clock pulses and having a frequency n times the frequency of the first clock pulses, wherein n represents a positive integer not smaller than 2; quasi-intermediate color generating means for superimposing the first clock pulses on a given image signal to provide a superimposed image signal and also for digitizing the superimposed image signal to provide a digitized signal; and memory means for sampling and storing the digitized signal from said quasi-intermediate color generating means when the second clock pulses from said clock pulse generating means are applied as sampling clock pulses.

Claim 4

Dependent Claim 117 words

An image signal processor comprising: clock pulse generating means for generating first clock pulses and also for generating second clock pulses synchronized with the first clock pulses and having a frequency n times the frequency of the first clock pulses, wherein n represents a positive integer not smaller than 2; quasi-intermediate color generating means for superimposing the first clock pulses on a given image signal to provide a superimposed image signal and also for digitizing the superimposed image signal to provide a digitized signal; and memory means for sampling and storing the digitized signal from said quasi-intermediate color generating means when the second clock pulses from said clock pulse generating means are applied as sampling clock pulses.

Claim 5

Dependent Claim 37 words

An image signal processor as in claim 2, wherein: said first clock pulses are superimposed on a portion of said given image signal, said portion being substantially equal to an average level of said given image signal.

Claim 6

Dependent Claim 60 words

An image signal processor comprising: quasi-intermediate color generating means for superimposing clock signals on a luminance signal, a clock pulse superimposing circuit having a direct current inhibiting means for cutting off a direct current component contained in the clock pulses; and a matrix circuit for summing the superimposed luminance signal and color difference signals together to provide an added output.

Claim 7

Dependent Claim 60 words

An image signal processor comprising: quasi-intermediate color generating means for superimposing clock signals on a luminance signal, a clock pulse superimposing circuit having a direct current inhibiting means for cutting off a direct current component contained in the clock pulses; and a matrix circuit for summing the superimposed luminance signal and color difference signals together to provide an added output.

Claim 8

Dependent Claim 20 words

The image signal processor as claimed in claim 4, further comprising: an analog-to-digital converting circuit for digitizing the added output.

Claim 9

Dependent Claim 17 words

An image signal processor as in claim 4, wherein said direct current inhibiting means comprises a capacitor.

Claim 10

Dependent Claim 66 words

An image signal processor as in claim 6, wherein said clock pulse superimposing circuit further includes: a transistor having a base to which a luminance signal is applied and to which the clock pulses are applied through the direct current inhibiting means, said transistor having a collector from which a superimposed luminance signal which corresponds to the luminance signal superimposed with the clock pulses is outputted.

Claim 11

Dependent Claim 96 words

An image signal processor comprising: a direct current amplifier for receiving an image signal descriptive of a still picture and clock pulses, a direct current component of said clock pulses having been cut off previously, and operable to superimpose said clock pulses on a portion of the image signal; an analog-to-digital converter for sampling an output from said direct current amplifier circuit at a timing smaller than the cycle of the clock pulses and thereafter converting the sampled output into a digital signal; and memory means for storing the digital signal outputted from said converter circuit.

Claim 12

Dependent Claim 96 words

An image signal processor comprising: a direct current amplifier for receiving an image signal descriptive of a still picture and clock pulses, a direct current component of said clock pulses having been cut off previously, and operable to superimpose said clock pulses on a portion of the image signal; an analog-to-digital converter for sampling an output from said direct current amplifier circuit at a timing smaller than the cycle of the clock pulses and thereafter converting the sampled output into a digital signal; and memory means for storing the digital signal outputted from said converter circuit.

Claim 13

Dependent Claim 33 words

An image signal processor as in claim 8, wherein: said portion of said image signal, upon which said clock pulses are superimposed, being substantially equal to an average level of said image signal.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-11-14	1998-05-16	1998-11-15	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-11-14	2002-05-16	2002-11-15	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-11-14	2006-05-16	2006-11-15	$7700.00	Window Closed / Lapsed

Image signal processor generating reduced memory consumption still images yet preserving image quality

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