US5365202A
Expired / Lapsed
US
⏱️ 0.0 years remaining
PLL frequency synthesizer using plural phase comparisons
Assignee: Mitsubishi Electric Corp
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Filing: 1993-03-30
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Granted: 1994-11-15
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Expires: 2013-03-30
Abstract
Abstract In a phase locked loop frequency synthesizer having multiple feedback loops, a reference phase signal is developed into two signals having a frequency twice as high as the reference frequency and the phase difference of the two signals is a half wavelength. The output frequency produced by a voltage-controlled oscillator is divided by two frequency dividers in accordance with predetermined frequency division factors. Each of the frequency-divided signals and each of the developed signals are subjected to phase comparison in pairs. A voltage signal corresponding to the phase differences is fed through a low-pass filter and supplied to the voltage-controlled oscillator.
Inventors
- 👤 Kazuhiro Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:21
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; H03L7/16; H03L7/18; H03L7/183
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
350 words
A frequency synthesizer using a phase-locked loop for producing signals of multiple frequencies, comprising: a voltage-controlled oscillator which generates a signal having a frequency correspondent to an input voltage supplied thereto; a reference signal oscillator which generates a first reference phase signal that establishes an operational base of said synthesizer; a phase distributor which produces a second reference phase signal and a third reference phase signal based on said first reference phase signal; a first frequency divider which divides an output frequency of said voltage-controlled oscillator by a first frequency division factor; a second frequency divider which divides an output frequency of said voltage-controlled oscillator by a second frequency division factor; a first phase comparator which detects a phase difference between the second reference phase signal and an output signal of said first frequency divider to produce a first phase difference signal which represents the detected phase difference; a second phase comparator which detects a phase difference between the third reference phase signal and an output signal of said second frequency divider to produce a second phase difference signal which represents the detected phase difference; an adder which adds the first and the second phase difference signals; a charge pump which varies an output state thereof in response to an output of said adder; and a low pass filter which removes the high frequency components above a predetermined frequency from an output signal of said charge pump and supplies a resulting voltage signal to said voltage-controlled oscillator; said first reference phase signal having a frequency twice as high as the frequency of the second and third reference phase signals; the phase difference between the second reference signal and the third reference signal being a half wavelength of the first reference signal; and wherein said first frequency divider produces a pulse signal on completion of counting N output pulses of said voltage-controlled oscillator, where N is a natural number representing a frequency division factor, and said second frequency divider produces a pulse signal on completion of counting (2n+1) N/2 output pulses of said voltage-controlled oscillator, where n is a natural number.
Claim 2
Dependent Claim
350 words
A frequency synthesizer using a phase-locked loop for producing signals of multiple frequencies, comprising: a voltage-controlled oscillator which generates a signal having a frequency correspondent to an input voltage supplied thereto; a reference signal oscillator which generates a first reference phase signal that establishes an operational base of said synthesizer; a phase distributor which produces a second reference phase signal and a third reference phase signal based on said first reference phase signal; a first frequency divider which divides an output frequency of said voltage-controlled oscillator by a first frequency division factor; a second frequency divider which divides an output frequency of said voltage-controlled oscillator by a second frequency division factor; a first phase comparator which detects a phase difference between the second reference phase signal and an output signal of said first frequency divider to produce a first phase difference signal which represents the detected phase difference; a second phase comparator which detects a phase difference between the third reference phase signal and an output signal of said second frequency divider to produce a second phase difference signal which represents the detected phase difference; an adder which adds the first and the second phase difference signals; a charge pump which varies an output state thereof in response to an output of said adder; and a low pass filter which removes the high frequency components above a predetermined frequency from an output signal of said charge pump and supplies a resulting voltage signal to said voltage-controlled oscillator; said first reference phase signal having a frequency twice as high as the frequency of the second and third reference phase signals; the phase difference between the second reference signal and the third reference signal being a half wavelength of the first reference signal; and wherein said first frequency divider produces a pulse signal on completion of counting N output pulses of said voltage-controlled oscillator, where N is a natural number representing a frequency division factor, and said second frequency divider produces a pulse signal on completion of counting (2n+1) N/2 output pulses of said voltage-controlled oscillator, where n is a natural number.
Claim 3
Dependent Claim
357 words
A frequency synthesizer using a phase-locked loop for producing signals of multiple frequencies, comprising: a voltage-controlled oscillator which generates a signal having a frequency correspondent to an input voltage supplied thereto; a reference signal oscillator which generates a first reference phase signal that establishes an operational base of said synthesizer; a phase distributor which produces a second reference phase signal and a third reference phase signal based on said first reference phase signal; a first frequency divider which divides an output frequency of said voltage-controlled oscillator by a first frequency division factor; a second frequency divider which divides an output frequency of said voltage-controlled oscillator by a second frequency division factor; a first phase comparator which detects a phase difference between the second reference phase signal and an output signal of said first frequency divider to produce a first phase difference signal which represents the detected phase difference; a second phase comparator which detects a phase difference between the third reference phase signal and an output signal of said second frequency divider to produce a second phase difference signal which represents the detected phase difference; an adder which adds the first and the second phase difference signals; a charge pump which varies an output state thereof in response to an output of said adder; and a low pass filter which removes the high frequency components above a predetermined frequency from an output signal of said charge pump and supplies a resulting voltage signal to said voltage-controlled oscillator; said first reference phase signal having a frequency twice as high as the frequency of the second and third reference phase signals; the phase difference between the second reference signal and the third reference signal being a half wavelength of the first reference signal; and wherein said first frequency divider produces a pulse signal on completion of counting N output pulses of said voltage-controlled oscillator, where N is a natural number representing a frequency division factor, and said second frequency divider produces a pulse signal on completion of counting X+nN output pulses of said voltage-controlled oscillator, where X is an integer nearest to N/2, and n is a natural number.
Claim 4
Dependent Claim
357 words
A frequency synthesizer using a phase-locked loop for producing signals of multiple frequencies, comprising: a voltage-controlled oscillator which generates a signal having a frequency correspondent to an input voltage supplied thereto; a reference signal oscillator which generates a first reference phase signal that establishes an operational base of said synthesizer; a phase distributor which produces a second reference phase signal and a third reference phase signal based on said first reference phase signal; a first frequency divider which divides an output frequency of said voltage-controlled oscillator by a first frequency division factor; a second frequency divider which divides an output frequency of said voltage-controlled oscillator by a second frequency division factor; a first phase comparator which detects a phase difference between the second reference phase signal and an output signal of said first frequency divider to produce a first phase difference signal which represents the detected phase difference; a second phase comparator which detects a phase difference between the third reference phase signal and an output signal of said second frequency divider to produce a second phase difference signal which represents the detected phase difference; an adder which adds the first and the second phase difference signals; a charge pump which varies an output state thereof in response to an output of said adder; and a low pass filter which removes the high frequency components above a predetermined frequency from an output signal of said charge pump and supplies a resulting voltage signal to said voltage-controlled oscillator; said first reference phase signal having a frequency twice as high as the frequency of the second and third reference phase signals; the phase difference between the second reference signal and the third reference signal being a half wavelength of the first reference signal; and wherein said first frequency divider produces a pulse signal on completion of counting N output pulses of said voltage-controlled oscillator, where N is a natural number representing a frequency division factor, and said second frequency divider produces a pulse signal on completion of counting X+nN output pulses of said voltage-controlled oscillator, where X is an integer nearest to N/2, and n is a natural number.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-14 | 1998-05-16 | 1998-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-14 | 2002-05-16 | 2002-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-14 | 2006-05-16 | 2006-11-15 | $7700.00 | Window Closed / Lapsed |