EP0526227A2
Expired / Lapsed
EP
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Phase-locked loop
Assignee: NEC Corp
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Filing: 1992-07-31
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Granted: —
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Expires: 2012-07-31
Abstract
Abstract A phase-locked loop according to the present invention includes first and second frequency demultipliers, and a plurality of phase/frequency detectors. The first and second frequency demultipliers divide frequency of first and second signals by a predetermined number. Each of the plurality of phase/frequency detectors compares two signals supplied from the first and second frequency demultipliers. In accordance with a comparison result of the plurality of phase/frequency detectors, phase of the second signal is adjusted to be synchronized with the first signal.
Inventors
- 👤 Takashi Fujii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 08:40
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/191; H03L7/08; H03L7/085; H03L7/087
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
141 words
A phase-locked loop, comprising: a first frequency demultiplier for dividing an input signal into plural input divided signals, said plural input divided signals having a predetermined phase difference from others; a second frequency demultiplier for dividing an output signal into plural output divided signals, said plural output divided signals having said predetermined phase difference from others; plural phase comparator each comparing phases of two corresponding input and output divided signals selected from said plural input and output divided signals; means for adding output signals of said plural phase comparators: a loop filter for generating a voltage control signal by receiving an output signal of said adding means; and a voltage controlled oscillator for generating a phase synchronous output signal by receiving said voltage control signal, said phase synchronous output signal being said output signal to be divided by said second demultiplier.
Claim 2
Dependent Claim
88 words
A phase-locked loop, comprising: a first frequency demultiplier for dividing frequency of a first signal by a predetermined number "N"; a second frequency demultiplier for dividing frequency of a second signal by said predetermined number "N"; a plurality of comparators each comparing two signals supplied from said first and second frequency demultipliers; means for supplying a control signal in accordance with a digital output signal of said plurality of comparators; and an oscillator for generating said second signal having a phase adjusted in accordance with said control signal.
Claim 3
Dependent Claim
22 words
A phase-locked loop, according to claim 2 or 3, wherein: each of said first and second frequency demultipliers are of Johnson counter.
Claim 4
Dependent Claim
36 words
A phase-locked loop, according to claim 2 or 3, wherein: said oscillator is a voltage controlled oscillator which supplies said second signal having a phase controlled in accordance with a voltage level of said control signal.
Claim 5
Dependent Claim
53 words
A phase-locked loop, according to claim 2, 3 or 4, wherein: said control signal supplying means comprises: an adder for adding said digital output signals supplied from said plurality of comparator; and a loop filter comprising a charge pump for supplying a control signal in accordance with an output signal of said adder.
Claim 6
Dependent Claim
24 words
A phase-locked loop, according to claim 5, wherein: said adder comprises two OR gates supplied with output signals from said plurality of comparators, respectively.
Claim 7
Dependent Claim
39 words
A phase-locked loop, according to claim 2, 3 or 4, wherein: said control signal supplying means comprises: a plurality of charge pump each connected to said plurality of comparators, respectively, and outputs thereof are connected to common output line.
References Cited (Backward Citations)
No citation records indexed.
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