Direct sequential-bit variable length decoder

Claim 2

A receiver arrangement of a digital communication system for receiving a plurality of variable length code words in the form of serial bit-stream comprising: a variable length decoder (VLD) for directly receiving said serial bit-stream and for sequentially decoding each of said plurality of variable length code words into fixed-length data; a data storage means including a plurality of data banks for sequentially receiving and temporarily storing said fixed-length data therein; a digital communication processing means including a plurality of parallel processing means, each connecting to a corresponding data bank, wherein each of said data banks connected in parallel between said variable length decoder (VLD) and said digital communication processing means via said parallel processing means; and each of said plurality of parallel processing means processing in parallel said fixed-length data for generating a plurality of digital communication data at a higher rate than the speed of said sequential decoding performed by said variable length decoder (VLD) to perform a real-time communication function.

Claim 3

A high definition television (HDTV) receiver arrangement for receiving and processing a plurality of video data in variable length code words for display comprising: a variable-length decoder (VLD) for directly receiving said video data in serial bit-stream and for sequentially decoding each of said plurality of variable length code words into a fixed length data; a data storage means for sequentially receiving and temporarily storing said fixed-length data therein and said data storage means further including a plurality of data banks; a video-display data processing means for utilizing said fixed-length data from said data storage means for processing and generating a plurality of video display data; said video-display data processing means further includes a plurality parallel run-length decoding processing means for performing run-length decoding on said fixed-length data, each connecting to a corresponding data bank, wherein each of said data banks connected in parallel between said variable length decoder (VLD) and said video-display data processing means via said parallel run-length decoding processing means; and said video-display data processing means processing said fixed-length data for generating said plurality of video-display data at a rate which is higher than the speed of said sequential decoding performed by said variable length decoder (VLD) to perform a real-time video-display function.

Claim 4

A high definition television (HDTV) receiver arrangement for receiving and processing a plurality of video data in variable length code words for display comprising: a variable-length decoder (VLD) for directly receiving said video data in serial bit-stream and for sequentially decoding each of said plurality of variable length code words into a fixed length data; a data storage means for sequentially receiving and temporarily storing said fixed-length data therein and said data storage means further including a plurality of data banks; a video-display data processing means for utilizing said fixed-length data from said data storage means for processing and generating a plurality of video display data; said video-display data processing means further includes a plurality parallel run-length decoding processing means for performing run-length decoding on said fixed-length data, each connecting to a corresponding data bank, wherein each of said data banks connected in parallel between said variable length decoder (VLD) and said video-display data processing means via said parallel run-length decoding processing means; and said video-display data processing means processing said fixed-length data for generating said plurality of video-display data at a rate which is higher than the speed of said sequential decoding performed by said variable length decoder (VLD) to perform a real-time video-display function.

Claim 5

The high definition television (HDTV) receiver arrangement of claim 2 wherein: said variable length decoder receives said video data in serial bit-stream at a rate of approximately 20 MHz and generating said fixed-length data at a burst rate of approximately 10 Mhz; and said data storage means including six data banks and said video-display data processing means including six parallel run-length decoding processing means wherein each of said plurality data banks and parallel run-length decoding processing means has a burst system speed of approximately 12 MHz and said video-display data processing means have a constant system speed of approximately 70 Mhz.

Claim 6

The high definition television (HDTV) receiver arrangement of claim 3 wherein: said data banks of said data storage means include dynamic random access memory (DRAM) storage means.

Claim 7

The high definition television (HDTV) receiver arrangement of claim 2 wherein: said variable-length decoder (VLD) sequentially decoding each of said plurality of variable length code words into a fixed length data by utilizing a Huffman decode table.

Claim 8

A high definition television (HDTV) receiver arrangement for receiving and processing a plurality of video data in variable length code words for display comprising: a variable-length decoder (VLD) for directly receiving said video data in serial bit-stream and for sequentially decoding each of said plurality of variable length code words into a fixed length data by utilizing a Huffman decoding table wherein said variable length decoder receives said video data in serial bit-stream at a rate of approximately 20 MHz and generating said fixed-length data at a burst rate of approximately 10 Mhz; a data storage means for sequentially receiving and temporarily storing said fixed-length data therein and said data storage means further including six DRAM data banks; a video-display data processing means for utilizing said fixed-length data from said data storage means for processing and generating a plurality of video display data; said video-display data processing means further includes six parallel run-length decoding processing means for performing run-length decoding on said fixed-length data, each connecting to a corresponding data bank wherein each of said data banks connected in parallel between said variable length decoder (VLD) and said video-display data processing means via said parallel run-length decoding processing means; each of said plurality data banks and parallel run-length decoding processing means has a burst system speed of approximately 12 MHz; and said video-display data processing means processing said fixed-length data for generating said plurality of video-display data at a rate of approximately 70 MHz to perform a real-time video-display function.

Claim 9

A high definition television (HDTV) receiver arrangement for receiving and processing a plurality of video data in variable length code words for display comprising: a variable-length decoder (VLD) for directly receiving said video data in serial bit-stream and for sequentially decoding each of said plurality of variable length code words into a fixed length data by utilizing a Huffman decoding table wherein said variable length decoder receives said video data in serial bit-stream at a rate of approximately 20 MHz and generating said fixed-length data at a burst rate of approximately 10 Mhz; a data storage means for sequentially receiving and temporarily storing said fixed-length data therein and said data storage means further including six DRAM data banks; a video-display data processing means for utilizing said fixed-length data from said data storage means for processing and generating a plurality of video display data; said video-display data processing means further includes six parallel run-length decoding processing means for performing run-length decoding on said fixed-length data, each connecting to a corresponding data bank wherein each of said data banks connected in parallel between said variable length decoder (VLD) and said video-display data processing means via said parallel run-length decoding processing means; each of said plurality data banks and parallel run-length decoding processing means has a burst system speed of approximately 12 MHz; and said video-display data processing means processing said fixed-length data for generating said plurality of video-display data at a rate of approximately 70 MHz to perform a real-time video-display function.