US5138315A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arrangements for variable-length encoding and decoding of digital signals
Assignee: US Philips Corp
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Filing: 1991-01-28
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Granted: 1992-08-11
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Expires: 2011-01-28
Abstract
Abstract Arrangement for variable-length encoding of digital signals, divided into N parallel paths, comprising a routing circuit which, after classification of the encoded signals in accordance with their lengths and classification of the buffer memories in accordance with their filling states, apply those signals to the buffer memories which are less filled as said signals are longer, said routing circuit being arranged between a variable-length encoding circuit and rate control circuit. The corresponding decoding arrangement, which receives said encoded signals in regrouped data blocks accompanied by a respective path indicator for said blocks, comprises, at the output of an inverse quantization circuit, a circuit for routing said blocks as a function of the associated path indicator.
Inventors
- 👤 Marcel Le Queau
- 👤 Jean-Jacques Lhuillier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:10
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03M7/40; H04; H04N; H04N19/00; G; G06; G06F; G06F5/00; G06F5/06; G06F5/065; H03M7/42; H04N19/10; H04N19/134; H04N19/146; H04N19/152; H04N19/30; H04N19/37; H04N19/42; H04N19/436; H04N19/90; H04N19/98; H04N19/50
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
140 words
An arrangement for variable-length encoding digital signals having a signal input and a signal output, said arrangement comprising: a) N parallel paths having N path inputs coupled to said signal input, and N path outputs providing N output signals, where N is an integer, each path comprising: i. means for quantizing said digital signals so as to provide quantized signals; and ii. means for variable-length encoding said quantized signals so as to provide encoded signals; b) rate control means coupled to said signal output, comprising a plurality of buffer memories; and c) routing means disposed between said N path outputs and said rate control means, for applying each of said encoded signals to a respective one of said buffer memories selected on the basis of the length of each respective encoded signal and respective filling states of said buffer memories.
Claim 2
Dependent Claim
140 words
An arrangement for variable-length encoding digital signals having a signal input and a signal output, said arrangement comprising: a) N parallel paths having N path inputs coupled to said signal input, and N path outputs providing N output signals, where N is an integer, each path comprising: i. means for quantizing said digital signals so as to provide quantized signals; and ii. means for variable-length encoding said quantized signals so as to provide encoded signals; b) rate control means coupled to said signal output, comprising a plurality of buffer memories; and c) routing means disposed between said N path outputs and said rate control means, for applying each of said encoded signals to a respective one of said buffer memories selected on the basis of the length of each respective encoded signal and respective filling states of said buffer memories.
Claim 3
Dependent Claim
89 words
The arrangement as claimed in claim 1, wherein each of said buffer memories provides a buffer memory signal output and wherein said arrangement further comprises: a) means coupled to said signal input, for demultiplexing a sequence of input signals into N digital signals, said demultiplexing means having N parallel outputs each coupled to one of said N path inputs; and b) means coupled to said rate control means, for multiplexing a plurality of said buffer memory output signals so as to provide a data output to said signal output.
Claim 4
Dependent Claim
29 words
An encoding arrangement as claimed in claim 2, wherein the rate control means comprises a single feedback connection connecting any one of the buffer memories to said quantization means.
Claim 5
Dependent Claim
45 words
The arrangement as claimed in claim 2, wherein each of said paths further comprises means, disposed between said variable-length encoding means and said N path outputs, for providing for each respective path, a delay to ensure synchronism of said encoded signals with said routing means.
Claim 6
Dependent Claim
25 words
The arrangement as claimed in claim 2, wherein said data output is provided as a sequence of data blocks each comprising an associated path indicator.
Claim 7
Dependent Claim
129 words
An arrangement for decoding the data blocks described in claim 5, said arrangement comprising: a) means for demultiplexing said sequence of data blocks into N data block signals; b) N parallel decoding paths each coupled to said demultiplexing means so as to receive one of said N data block signals, each path comprising: i. means for storing data blocks so as to provide stored encoded signals; ii. means for variable-length decoding said stored data block signals so as to provide decoded signals; and iii. means for inverse quantizing said decoded signals so as to provide decoded data blocks at a respective decoded path output; c) means coupled to each said decoded path output, for routing each of said decoded data blocks as a function of the associated path indicator.
Claim 8
Dependent Claim
98 words
The arrangement of claim 6, wherein said routing means comprises: a) a switching circuit having N switches, each switch having a switch input coupled to one of said decoded path outputs, and N switch outputs; and b) a transcoding circuit comprising N transcoding elements each having an input coupled to one of said decoded path outputs for receiving the associated path indicators of decoded data blocks, and an output coupled to a respective one of said switches so as to couple each decoded data block to a selected witch output as a function of the associated path indicator.
Claim 9
Dependent Claim
34 words
The arrangement of claim 7, wherein said routing means further comprises N delay circuits, each of said delay circuits being coupled between one of said decoded path outputs and one of said switch inputs.
Claim 10
Dependent Claim
39 words
The arrangement of claim 8 further comprising means coupled to each of said switch outputs, for multiplexing said decoded data blocks so as to form a continuous sequence of data blocks arrange in accordance with respective associated path indicators.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-11 | 1996-02-10 | 1996-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-11 | 2000-02-10 | 2000-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-11 | 2004-02-10 | 2004-08-11 | $7700.00 | Window Closed / Lapsed |