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US5363058A Expired / Lapsed US ⏱️ 0.0 years remaining

Amplifier having linear input-output characteristics and high efficiency

Assignee: Mitsubishi Electric Corp
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Filing: 1993-03-11
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Granted: 1994-11-08
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Expires: 2013-03-11
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Abstract

Abstract An amplifier for amplifying a high frequency signal includes an input impedance matching circuit; an output impedance matching circuit; an FET having a gate and a drain connected to the input impedance matching circuit and the output impedance matching circuit, respectively; and a gate voltage control circuit for controlling the gate voltage of the FET in response to the power of the high frequency signal. The gate voltage control circuit includes a diode having an anode connected to the gate, a capacitor connected between the cathode of the diode and ground, and a gate bias setting circuit connected to the junction of the diode and the capacitor. The gate bias setting circuit outputs a control voltage corresponding to the power of the high frequency signal. As a result, impedance matching by the output matching circuit is not disturbed and the linearity of the output power to the input power is maintained so that the amplifier operates highly efficiently.

Inventors

  • 👤 Yoshinobu Sasaki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 14:50
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/02; H03F1/0205; H03F1/0261; H03F1/0266; H03F1/30; H03F1/301; H03F1/306; H03F1/32; H03F1/3205; H03F1/3223; H03F2200/00; H03F2200/18; H03F2200/192; H03F2200/222; H03F2200/228; H03F2200/255; H03F2200/387; H03F2200/423; H03F2200/48; H03F2200/75

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 209 words
An amplifier for amplifying a high frequency signal comprising: an input impedance matching circuit having an input end and an output end; an output impedance matching circuit having an input end and an output end; an FET having a gate connected to the output end of said input impedance matching circuit for receiving a high frequency signal having a power for amplification by said FET and a drain connected to the input end of said output impedance matching circuit; and a gate voltage control circuit for controlling a gate voltage applied to the gate of said FET in response to the power of the high frequency signal, an output of said gate voltage control circuit being connected to a junction of the output end of said input impedance matching circuit and the gate of said FET, said gate voltage control circuit comprising a diode having an anode and a cathode, the anode being connected to the gate of said FET, a capacitor connected between the cathode of said diode and ground, and a gate bias setting circuit having an output terminal connected to the junction of the cathode of said diode and said capacitor for outputting a control voltage in response to the power of the high frequency signal.
Claim 2
Dependent Claim 209 words
An amplifier for amplifying a high frequency signal comprising: an input impedance matching circuit having an input end and an output end; an output impedance matching circuit having an input end and an output end; an FET having a gate connected to the output end of said input impedance matching circuit for receiving a high frequency signal having a power for amplification by said FET and a drain connected to the input end of said output impedance matching circuit; and a gate voltage control circuit for controlling a gate voltage applied to the gate of said FET in response to the power of the high frequency signal, an output of said gate voltage control circuit being connected to a junction of the output end of said input impedance matching circuit and the gate of said FET, said gate voltage control circuit comprising a diode having an anode and a cathode, the anode being connected to the gate of said FET, a capacitor connected between the cathode of said diode and ground, and a gate bias setting circuit having an output terminal connected to the junction of the cathode of said diode and said capacitor for outputting a control voltage in response to the power of the high frequency signal.
Claim 3
Dependent Claim 82 words
The amplifier of claim 1 wherein said gate bias setting circuit comprises a distributor for extracting part of the power of the high frequency signal, a power detector connected to said distributor for detecting the power extracted by said distributor and outputting a detector signal in response, and a voltage generator connected to said power detector for outputting a control voltage corresponding to the detector signal of said power detector to the junction of the cathode of said diode and said capacitor.
Claim 4
Dependent Claim 15 words
The amplifier of claim 1 wherein said high frequency signal is at least one GHz.

References Cited (Backward Citations)

US4268797A Cited
EP0033198A1 Cited
US4320352A Cited
FR2523782A1 Cited
JPS61103307A Cited
JPS61296804A Cited
JPS63202107A Cited
JPH02149108A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-11-07 1998-05-09 1998-11-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-11-07 2002-05-09 2002-11-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-11-07 2006-05-09 2006-11-08 $7700.00 Window Closed / Lapsed

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