US4320352A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input optimized FET bias circuit
Assignee: Lanteris Space LLC
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Filing: 1980-01-29
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Granted: 1982-03-16
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Expires: 2000-01-29
Abstract
Abstract A field effect transistor bias circuit is presented which exhibits a low impedance for small signals and a high impedance for large signals. This circuit uses an operational amplifier to provide a temperature compensated low impedance voltage source for the gate bias which is optimal for small signal operation. In the presence of a large signal, the gate begins to draw current. This causes the operational amplifier to saturate and transforms the bias circuit into a high impedance source, which is optimal for large signal operation.
Inventors
- 👤 Michael D. Rubin
- 👤 Pang T. Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:27
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/301; H03F1/02; H03F1/0205; H03F1/0261; H03G; H03G3/00; H03G3/20; H03G3/30; H03F2200/00; H03F2200/18
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
94 words
An adaptive gate bias circuit for a field effect transistor having a gate, a drain, and a source, comprising: a bias reference voltage; an operational amplifier having a first input connected to the bias reference voltage; and a first resistance connected between the output of the amplifier and the gate of the FET; wherein said operational amplifier is not connected to said drain and is not connected to said source; wherein said circuit changes the bias voltage on the gate as a function of the amplitude of an input signal coupled to the gate.
Claim 2
Dependent Claim
94 words
An adaptive gate bias circuit for a field effect transistor having a gate, a drain, and a source, comprising: a bias reference voltage; an operational amplifier having a first input connected to the bias reference voltage; and a first resistance connected between the output of the amplifier and the gate of the FET; wherein said operational amplifier is not connected to said drain and is not connected to said source; wherein said circuit changes the bias voltage on the gate as a function of the amplitude of an input signal coupled to the gate.
Claim 3
Dependent Claim
24 words
The circuit of claim 1 further comprising a second resistance connected between a second input of the amplifier and the gate of the FET.
Claim 4
Dependent Claim
23 words
The circuit of claim 1 wherein the amplifier compensates for voltage disparity between the signal applied at the gate and the reference voltage.
Claim 5
Dependent Claim
38 words
The circuit of claim 1 wherein the amplifier saturates due to the presence of a large input signal applied to the gate, causing the bias circuit to behave as a fixed voltage in series with the first resistance.
Claim 6
Dependent Claim
23 words
The circuit of claim 1 wherein said first resistance is connected to said gate via a decoupling network; and said source is grounded.
Claim 7
Dependent Claim
21 words
A circuit as recited in claim 1 further comprising voltage limiting means connected to said gate to limit the voltage thereon.
Claim 8
Dependent Claim
31 words
A circuit as recited in claim 6 wherein said voltage limiting means comprises: a fail safe reference voltage; and a diode connected between the fail safe reference voltage and said gate.
Claim 9
Dependent Claim
23 words
A circuit as recited in claim 1 wherein the bias reference voltage is temperature compensated; wherein said signal is an alternating current signal.
Claim 10
Dependent Claim
30 words
A circuit as recited in claim 1 further comprising a Zener diode, connected between the output of the operational amplifier and ground, for limiting the output voltage of the amplifier.
Claim 11
Dependent Claim
48 words
A circuit as recited in claim 1 wherein the field effect transistor is a N-channel depletion mode FET and the bias reference voltage is negative; wherein said operational amplifier has a positive and a negative input and the first input of the operational amplifier is the positive input.
Claim 12
Dependent Claim
32 words
A circuit as recited in claim 1 wherein the bias reference voltage compensates for temperature sensitive characteristics of the FET; wherein said signal does not pass through said adaptive gate bias circuit.
Claim 13
Dependent Claim
79 words
A circuit for adaptively biasing a field effect transistor having a gate, a drain, and a source, comprising: reference bias voltage means; and a voltage follower having an input connected to the reference bias voltage means and an output connected via a bias decoupling network to the gate of the FET; wherein the voltage follower provides a low impedance voltage source when it is not in saturation, and provides a high impedance voltage source when it is in saturation.
Claim 14
Dependent Claim
79 words
A circuit for adaptively biasing a field effect transistor having a gate, a drain, and a source, comprising: reference bias voltage means; and a voltage follower having an input connected to the reference bias voltage means and an output connected via a bias decoupling network to the gate of the FET; wherein the voltage follower provides a low impedance voltage source when it is not in saturation, and provides a high impedance voltage source when it is in saturation.
Claim 15
Dependent Claim
110 words
A bias circuit for a field effect transistor having a gate, a drain, and a source, comprising: a bias reference voltage; an operational amplifier having a first input connected to the bias reference voltage; and a first resistance connected between the output of the amplifier and the gate of the field effect transistor; wherein the value of said first resistance is sufficient to limit the gate current of the transistor and yet is not so large as to compromise the ability of the amplifier to compensate for the effect of any transistor leakage current; wherein said amplifier is not connected to said source and is not connected to said drain.
Claim 16
Dependent Claim
110 words
A bias circuit for a field effect transistor having a gate, a drain, and a source, comprising: a bias reference voltage; an operational amplifier having a first input connected to the bias reference voltage; and a first resistance connected between the output of the amplifier and the gate of the field effect transistor; wherein the value of said first resistance is sufficient to limit the gate current of the transistor and yet is not so large as to compromise the ability of the amplifier to compensate for the effect of any transistor leakage current; wherein said amplifier is not connected to said source and is not connected to said drain.
Claim 17
Dependent Claim
37 words
The circuit of claim 13 further comprising: a feedback resistance having a value much larger than that of the first resistance; wherein said feedback resistance is connected between the gate and a second input of the amplifier.
References Cited (Backward Citations)
JPS5237751A
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JPS5256844A
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US4077013A
Cited
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US4152666A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-03-15 | 1985-09-14 | 1986-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-03-15 | 1989-09-14 | 1990-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-03-15 | 1993-09-14 | 1994-03-16 | $7700.00 | Window Closed / Lapsed |