Patent US5361341A successfully refreshed from Google Patents.
US5361341A
Expired / Lapsed
US
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Device for enabling the use of the contents of memory areas of an electronic microprocessor system
Assignee: STMicroelectronics SA
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Filing: 1993-02-10
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Granted: 1994-11-01
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Expires: 2013-02-10
Abstract
Abstract A decision circuit receives input addresses of instructions to be executed and data addresses to which the instructions are to be applied. The decision circuit either allows the execution of the instruction or prohibits the execution of the instruction if the instruction leads to a false operation or to a fraudulent attempt to divulge the system contents. A buffer register stores the instruction addresses and subsequently presents them to the decision circuit simultaneously with the data addresses. This device applies particularly to the protection of electronic integrated circuit memory cards.
Inventors
- 👤 Laurent Sourgen
- 👤 Rodolphe Uhlmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:11
CPC Classifications
G; G07; G07F; G07F7/00; G07F7/08; G07F7/10; G07F7/1008; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1441; G06Q; G06Q20/00; G06Q20/30; G06Q20/34; G06Q20/341; G06Q20/357
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
273 words
An integrated circuit memory address protection device, comprising: a plurality of flip-flops connected to receive a respective plurality of decoded address lines, and having a clock input connected to receive a first signal; a corresponding plurality of static gates which are also connected, in parallel to said flip-flops, to receive said respective plurality of decoded address lines, and connected to receive a second signal at an enable input, and configured and connected to drive a respective plurality of output lines in accordance with the state of said address lines and said second signal; an validation circuit having an input connection, and configured to output an error signal whenever said input connection is driven toward a predetermined first voltage; a plurality of pass transistors each connected to receive a respective one of said output lines of said static gates at a respective control terminal thereof, and each connected between said error-detection circuit and a respective one of a plurality of first connections; and a programmed array, including a plurality of first lines each connected to a respective output of one of said flip-flops, and a plurality of second lines each connected to a respective one of said first connections, and a plurality of transistors, at some BUT NOT ALL intersections of said first and second lines, each having a respective control terminal connected to a respective one of said first lines, and each having respective current-conducting terminals connected to drive a respective one of said second lines toward said first voltage; whereby the locations of transistors in said array determine which combinations of addresses will cause said validation circuit to produce an error signal.
Claim 2
Dependent Claim
273 words
An integrated circuit memory address protection device, comprising: a plurality of flip-flops connected to receive a respective plurality of decoded address lines, and having a clock input connected to receive a first signal; a corresponding plurality of static gates which are also connected, in parallel to said flip-flops, to receive said respective plurality of decoded address lines, and connected to receive a second signal at an enable input, and configured and connected to drive a respective plurality of output lines in accordance with the state of said address lines and said second signal; an validation circuit having an input connection, and configured to output an error signal whenever said input connection is driven toward a predetermined first voltage; a plurality of pass transistors each connected to receive a respective one of said output lines of said static gates at a respective control terminal thereof, and each connected between said error-detection circuit and a respective one of a plurality of first connections; and a programmed array, including a plurality of first lines each connected to a respective output of one of said flip-flops, and a plurality of second lines each connected to a respective one of said first connections, and a plurality of transistors, at some BUT NOT ALL intersections of said first and second lines, each having a respective control terminal connected to a respective one of said first lines, and each having respective current-conducting terminals connected to drive a respective one of said second lines toward said first voltage; whereby the locations of transistors in said array determine which combinations of addresses will cause said validation circuit to produce an error signal.
Claim 3
Dependent Claim
15 words
The memory address protective device of claim 1, wherein said first voltage is ground voltage.
Claim 4
Dependent Claim
16 words
The memory address protective device of claim 1, wherein said static logic gates are AND gates.
Claim 5
Dependent Claim
36 words
The memory address protection device of claim 1, further comprising decoding logic connected to receive at least two high-order address bits and configured to generate said decoded address lines in accordance with said high-order address bits.
Claim 6
Dependent Claim
30 words
The memory address protection device of claim 1, wherein said validation circuit comprises an electrical load connected to drive the potential of said input connection away from said first voltage.
Claim 7
Dependent Claim
19 words
The memory address protection device of claim 1, wherein said decoded address lines correspond to high-order memory address bits.
Claim 8
Dependent Claim
26 words
The memory address protection device of claim 1, in combination with a microprocessor core which is connected to receive said error signal from said validation circuit.
Claim 9
Dependent Claim
47 words
The memory address protection device of claim 1, in combination with a memory which is also connected to receive said address bits, and a microprocessor which is connected to control access to said memory and is also connected to receive said error signal from said validation circuit.
Claim 10
Dependent Claim
209 words
An integrated circuit memory address protection device, comprising: a clocked buffer connected to receive a respective plurality of decoded address lines, and connected to receive a first signal at a clock input thereof; an validation circuit having an input connection, and configured to output an error signal whenever said input connection is driven toward a predetermined first voltage; a plurality of pass transistors each operatively connected to receive a respective one of said decoded address lines at a respective control terminal thereof, and each connected between said error-detection circuit and a respective one of a plurality of first connections; and a programmed array, including a plurality of first lines each connected to a respective output of said clocked buffer, and a plurality of second lines each connected to a respective one of said first connections, and a plurality of transistors, at some BUT NOT ALL intersections of said first and second lines, each having a respective control terminal connected to a respective one of said first lines, and having respective current-conducting terminals connected to drive a respective one of said second lines toward said first voltage; whereby the locations of transistors in said array determine which combinations of addresses will cause said validation circuit to produce an error signal.
Claim 11
Dependent Claim
209 words
An integrated circuit memory address protection device, comprising: a clocked buffer connected to receive a respective plurality of decoded address lines, and connected to receive a first signal at a clock input thereof; an validation circuit having an input connection, and configured to output an error signal whenever said input connection is driven toward a predetermined first voltage; a plurality of pass transistors each operatively connected to receive a respective one of said decoded address lines at a respective control terminal thereof, and each connected between said error-detection circuit and a respective one of a plurality of first connections; and a programmed array, including a plurality of first lines each connected to a respective output of said clocked buffer, and a plurality of second lines each connected to a respective one of said first connections, and a plurality of transistors, at some BUT NOT ALL intersections of said first and second lines, each having a respective control terminal connected to a respective one of said first lines, and having respective current-conducting terminals connected to drive a respective one of said second lines toward said first voltage; whereby the locations of transistors in said array determine which combinations of addresses will cause said validation circuit to produce an error signal.
Claim 12
Dependent Claim
15 words
The memory address protection device of claim 9, wherein said first voltage is ground voltage.
Claim 13
Dependent Claim
25 words
The memory address protection device of claim 9, further comprising logic gates connected to and interposed between said decoded address lines and said pass transistors.
Claim 14
Dependent Claim
36 words
The memory address protection device of claim 9, further comprising decoding logic connected to receive at least two high-order address bits and configured to generate said decoded address lines in accordance with said high-order address bits.
Claim 15
Dependent Claim
30 words
The memory address protection device of claim 9, wherein said validation circuit comprises an electrical load connected to drive the potential of said input connection away from said first voltage.
Claim 16
Dependent Claim
20 words
The memory address protection device of claim 9, wherein said clocked buffer comprises a plurality of flip-flops connected in parallel.
Claim 17
Dependent Claim
19 words
The memory address protection device of claim 9, wherein said decoded address lines correspond to high-order memory address bits.
Claim 18
Dependent Claim
26 words
The memory address protection device of claim 9, in combination with a microprocessor core which is connected to receive said error signal from said validation circuit.
Claim 19
Dependent Claim
47 words
The memory address protection device of claim 9, in combination with a memory which is also connected to receive said address bits, and a microprocessor which is connected to control access to said memory and is also connected to receive said error signal from said validation circuit.
Claim 20
Dependent Claim
167 words
An integrated circuit memory address protection device, comprising: a clocked buffer connected to receive a respective plurality of decoded address lines, and connected to receive a first signal at a clock input thereof; an validation circuit having an input connection, and configured to output an error signal whenever said input connection is driven toward a predetermined first voltage; a plurality of pass transistors each having a respective control terminal operatively connected to a respective one of said decoded address lines, and each connected between said error-detection circuit and a respective one of a plurality of first connections; and a programmed array, including a plurality of first lines each connected to a respective output of said clocked buffer, and a plurality of second lines each connected to a respective one of said first connections, and, at some BUT NOT ALL intersections of said first and second lines, connections such that said respective second line will be driven toward said first voltage whenever said respective first line is active.
Claim 21
Dependent Claim
167 words
An integrated circuit memory address protection device, comprising: a clocked buffer connected to receive a respective plurality of decoded address lines, and connected to receive a first signal at a clock input thereof; an validation circuit having an input connection, and configured to output an error signal whenever said input connection is driven toward a predetermined first voltage; a plurality of pass transistors each having a respective control terminal operatively connected to a respective one of said decoded address lines, and each connected between said error-detection circuit and a respective one of a plurality of first connections; and a programmed array, including a plurality of first lines each connected to a respective output of said clocked buffer, and a plurality of second lines each connected to a respective one of said first connections, and, at some BUT NOT ALL intersections of said first and second lines, connections such that said respective second line will be driven toward said first voltage whenever said respective first line is active.
Claim 22
Dependent Claim
15 words
The memory address protection device of claim 18, wherein said first voltage is ground voltage.
Claim 23
Dependent Claim
25 words
The memory address protection device of claim 18, further comprising logic gates connected to and interposed between said decoded address lines and said pass transistors.
Claim 24
Dependent Claim
36 words
The memory address protection device of claim 18, further comprising decoding logic connected to receive at least two high-order address bits and configured to generate said decoded address lines in accordance with said high-order address bits.
Claim 25
Dependent Claim
30 words
The memory address protection device of claim 18, wherein said validation circuit comprises an electrical load connected to drive the potential of said input connection away from said first voltage.
Claim 26
Dependent Claim
19 words
The memory address protection device of claim 18, wherein said decoded address line correspond to high-order memory address bits.
Claim 27
Dependent Claim
20 words
The memory address protection device of claim 18, wherein said clocked buffer comprises a plurality of flip-flops connected in parallel.
Claim 28
Dependent Claim
26 words
The memory address protection device of claim 18, in combination with a microprocessor core which is connected to receive said error signal from said validation circuit.
Claim 29
Dependent Claim
47 words
The memory address protection device of claim 18, in combination with a memory which is also connected to receive said address bits, and a microprocessor which is connected to control access to said memory and is also connected to receive said error signal from said validation circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |