Method and apparatus for clock distribution and for distributed clock synchronization

Claim 2

A clock distribution apparatus for use in providing a common absolute time reference to spatially distributed application modules requiring synchronized clocks, said apparatus comprising: means for transmitting an outgoing reference signal from a first site to a second site and a return reference signal from said second site to said first site upon arrival of said outgoing reference signal at said second site; and means at each said application module for detecting an outgoing reference signal and a corresponding return reference signal and producing a local phase reference signal approximately midway through the time interval required for said outgoing reference signal to travel from a signal detecting site at said application module to said second site and said return reference signal to travel from said second site to said signal detecting site.

Claim 3

An clock synchronizing apparatus as defined in claim 1, said outgoing and return reference signals having having a maxing frequency given by: f.sub.pulser max =v/2D (3) where D=the distance from a detecting site to said second site; v=kc=propagation velocity; k<1 c=light propagation velocity in vacuum.

Claim 4

An clock synchronizing apparatus as defined in claim 2, further including, at each said application module, means responsive to said local phase reference signal for adjusting the phase of a local clock associated with said application module whereby to provide system-wide phase coherent synchronization of said application modules.

Claim 5

A clock synchronizing apparatus as defined in claim 3, further including means defining a reference signal reference path for said outgoing and said return reference signals, said reference path including an outgoing path for transmitting said outgoing reference signal therealong and a return path for transmitting said return reference signal therealong, each said application module having a signal detecting site in said reference path.

Claim 6

A clock synchronizing apparatus as defined in claim 4, said reference path comprising a pair of electrical conductors having substantially equal lengths from any point thereon to said second site and being routed as a pair to the location of every application module to be synchronized.

Claim 7

A clock synchronizing apparatus as defined in claim 4, said reference path comprising a single electrical conductor routed from said first site to said second site and through to the location of every application module to be synchronized.

Claim 8

A clock synchronizing apparatus as defined in claim 4, said reference path being a free-space electromagnetic radiation path.

Claim 9

A clock synchronizing apparatus as defined in claim 7, said electromagnetic radiation path including radio, lightwave, infrared or other high frequency electromagnetic radiation paths.

Claim 10

A clock synchronizing apparatus as defined in claim 7; and further including means at each said application module for compensating for non-planar electromagnetic wave fronts.

Claim 11

A clock synchronizing apparatus as defined in claim 7 said detecting means including radio antennas optical, infra-red photodiodes, and/or lens assemblies.

Claim 12

A clock synchronizing apparatus as defined in claim 3, further including means at said second site for emitting said return reference signal upon receipt of said outgoing reference signal.

Claim 13

A clock synchronizing apparatus as defined in claim 3, further including means at said second site for re-transmitting said outgoing reference signal as said return reference signal from said second site towards said first site upon receipt of said outgoing reference signal.

Claim 14

A clock synchronizing apparatus as defined in claim 3, said detecting means including interval-halving circuit means.

Claim 15

A clock synchronizing apparatus as defined in claim 13, said interval-halving circuit including: first detector means for producing a output signal upon detecting an outgoing reference signal; second detector means for producing a second output signal upon detecting a return reference signal; means responsive to said first and second output signals for determining and storing the time interval between said first and second output signals; and means responsive to said first output signal for comparing a current time interval with an immediately preceding time interval and producing a reference phase output signal when said current time interval is one half said preceding time interval.

Claim 16

A clock synchronizing apparatus as defined in claim 14, said determining and storing means including: ramp generator means responsive to said first output signal for producing an output linear voltage rise; and sample and hold gate means responsive to said second output signal for acquiring and storing said output of said ramp generator means.

Claim 17

A clock synchronizing apparatus as defined in claim 15, said means for producing said reference phase output signal including a rising edge short pulse generator means.

Claim 18

A clock synchronizing apparatus as defined in claim 2, said outgoing and return reference signals being isolated square wave pulses.

Claim 19

A clock transmitting apparatus as defined in claim 17, wherein said transmitting means is for producing pulses at an interval greater than the round trip propagation time of said reference signals.

Claim 20

A clock synchronizing apparatus as defined in claim 3, said responsive means being a local clock phase lock loop circuit means for locking onto said local phase reference signal.

Claim 21

A clock synchronizing apparatus as defined in claim 3, said means responsive to said local phase reference signal comprising a phase lock loop circuit means including a voltage controlled oscillator having an input and an output for producing an oscillator output signal at a frequency and phase determined by a voltage applied to said oscillator input, and divider means for receiving said oscillator output signal for producing POSITIVE and INVERTED output signals; said detector means including interval-halving circuit means operative to produce a pulse whose duration is equal to said time interval, means for receiving said POSITIVE and INVERTED output signals and said pulse for applying to said input of said voltage controlled oscillator a voltage proportional to the deviation of the transition between said POSITIVE and INVERTED outputs from the center point of said pulse.

Claim 22

A clock synchronizing apparatus as defined in claim 20, further including means for maintaining the voltage applied to said oscillator input at a constant value when there is no reference signal flowing between said detecting sites and said second site.

Claim 23

A clock synchronizing apparatus as defined in claim 20, said means for receiving said POSITIVE and INVERTED output signals and said predetermined output signal including: first and second AND gates, each having a pair of inputs and an output, one input of each said AND gate being connected to the output of said detector means, the other input of one of said AND gates for receiving said POSITIVE output and the other input of the other of said AND gates for receiving said INVERTED output; and first and second switch means having a common output connected to said oscillator input, one of said switch means for receiving the output of one of said AND gates and the other of said switch means for receiving the output of the other of said AND gates.

Claim 24

A clock synchronizing apparatus as defined in claim 22, each said switch means being an FET transmission gate.

Claim 25

A clock synchronizing apparatus as defined in claim 23, further including means for maintaining the voltage applied to said oscillator input at a constant value when there is no reference pulse flowing between said detecting sites and said second site.

Claim 26

A clock synchronizing apparatus as defined in claim 24, said maintaining means being a capacitor.

Claim 27

A clock synchronizing apparatus as defined in claim 25, said detector means being a set-reset flip flop.

Claim 28

A clock synchronizing apparatus as defined in claim 3, further including means for transmitting a raw clock signal to each said application module.

Claim 29

A clock synchronizing apparatus as defined in claim 27, further including means defining a raw clock signal transmission path to each said application module.

Claim 30

A clock synchronizing apparatus as defined in claim 28, said means responsive to said local phase reference signal comprising a phase lock loop circuit means including a phase shifter having a first input for receiving said raw clock signal, a second input for receiving said local phase reference signal and an output for delivering a phase aligned clock signal, and divider means adapted to receive said oscillator output signal for producing POSITIVE and INVERTED output signals; said detector means including interval-halving circuit means operative to produce a pulse whose duration is equal to said time interval, means for receiving said POSITIVE and INVERTED output signals and said pulse for applying to said input of said voltage controlled oscillator a voltage proportional to the deviation of the transition between said POSITIVE and INVERTED outputs from the center point of said pulse.

Claim 31

A clock synchronizing apparatus as defined in claim 29, said phase shifter being a digitally controllable, programmable phase shifter.

Claim 32

A clock synchronizing apparatus as defined in claim 29, said phase shifter being a continuously variable phase shifter.

Claim 33

A clock synchronizing apparatus as defined in claim 29, said means for receiving said POSITIVE and INVERTED output signals and said predetermined output signal including: first and second AND gates, each having a pair of inputs and an output, one input of each said AND gate being connected to the output of said detector means, the other input of one of said AND gates for receiving said POSITIVE output and the other input of the other of said AND gates for receiving said INVERTED output; and first and second switch means having a common output connected to said oscillator input, one of said switch means for receiving the output of one of said AND gates and the other of said switch means for receiving the output of the other of said AND gates.

Claim 34

A clock synchronizing apparatus as defined in claim 32, each said switch means being an FET transmission gate.

Claim 35

A clock synchronizing apparatus as defined in claim 33, said detector means being a set-reset flip flop.

Claim 36

A clock synchronizing apparatus as defined in claim 3, said means responsive to said local phase reference signal comprising a phase lock loop circuit means including a voltage controlled oscillator having an input and an output for producing an oscillator clock output signal at a frequency and phase determined by a voltage applied to said oscillator input, and divide-by-N circuit means for receiving said oscillator output signal for delivering a divider output; said detector means including interval-halving circuit means for controlling the voltage to applied to said oscillator, said interval-halving circuit means comprising: first and second counter means, each said counter means having a clock input for receiving the output of said oscillator, said first counter means having a first count output, a first input for receiving said outgoing reference signal and a second input for receiving said divider output and being enabled to count oscillator clock outputs by said outgoing reference signal and being disabled by said divider output; said second counter means having a second count output, a first input for receiving said divider output and a second input for receiving said return reference signal and being enabled to count oscillator outputs by said divider output and being disabled by said return reference signal; comparator means for comparing said first and second count outputs producing a first output when said first count output is greater than said second count output and a second output when said second count output is greater than said first count output; first buffer means responsive to said first comparator output for increasing the voltage applied to said oscillator whereby to increase the frequency of its output; and second buffer means responsive to said second comparator output for decreasing the voltage applied to said oscillator whereby to decrease the frequency of its output.

Claim 37

A clock synchronizing apparatus as defined in claim 3, said detecting means and said responsive means further including: a fixed frequency oscillator for producing clock signals at a predetermined frequency; a programmable divider circuit means for receiving said clock signals and having an output and divider first, second and third inputs; divide-by-N circuit means for receiving said programmable divider circuit means output for delivering a divider output; first and second counter means, each said counter means having a clock input for receiving said oscillator clock signals; said first counter means having a first count output, a first input for receiving said outgoing reference signal and a second input for receiving said divider output and being enabled to count oscillator clock outputs by said outgoing reference signal and being disabled by said divider output; said second counter means having a second count output, a first input for receiving said divider output and a second input for receiving said return reference signal and being enabled to count oscillator clock outputs by said divider output and being disabled by said return reference signal; comparator means for comparing said first and second count outputs delivering a first output to said first divider input when said first count output is greater than said second count output, a second output to said second divider input when said second count output is greater than said first count output and a third output to said third divider input when said second count output is equal to said first count output; said programmable divider circuit means being responsive to adjust the phase of its output to provide system-wide phase coherent synchronization of said application modules.

Claim 40

A method as defined in claim 37, wherein said transmitting step includes transmitting a signal at a predetermined frequency wherein the period thereof is greater than the round trip propagation time of said signals.

Claim 41

A method as defined in claim 38, said predetermined frequency being less than or equal to f.sub.pulser =v/2D where D is the length of said outgoing path v=kc=propagation velocity; k<1 c=propagation velocity of light in a vacuum.

Claim 42

A method as defined in claim 37, said predetermined frequency being less than or equal to f.sub.pulser =f.sub.hs /[floor}f.sub.hs 2D/v}] where: f hs is the frequency of the high-speed system clock; floor {arg} is a function that takes the largest integer less than {arg}; D is the length of said outgoing path; v=kc=propagation velocity; k<1; and c is the propagation velocity of light in a vacuum.

Claim 43

A method as defined in claim 37, further including the step of regenerating each said reference pulse at said remote site.

Claim 44

A method as defined in claim 37, further including the step of terminating and regenerating each said reference signals at the location of each application module extracting synchronism from said signals.

Claim 47

A method as defined in claim 43, wherein the period of said predetermined frequency is greater than the round trip propagation time of said pulses along said outgoing and return paths of said reference path.

Claim 48

A method as defined in claim 43, said predetermined frequency being less than or equal to f.sub.pulser =v/2D where D is the length of said outgoing path v=kc=propagation velocity; k<1 c=propagation velocity of light in a vacuum.

Claim 49

A method as defined in claim 43, said predetermined frequency being less than or equal to f.sub.pulser =f.sub.hs /[floor[f.sub.hs 2D/v}] where: f hs is the frequency of the high-speed system clock; floor {arg} is a function that takes the largest integer less than {arg}; D is the length of said outgoing path; v=kc=propagation velocity; k<1; and c is the propagation velocity of light in a vacuum.

Claim 50

A method as defined in claim 43, further including the step of regenerating each said reference pulse at said remote site.

Claim 51

A method as defined in claim 43, further including the step of terminating and regenerating each said reference pulses at the location of each application module extracting synchronism from said reference path.

Claim 52

A method as defined in claim 43, said outgoing and return paths having equal lengths from any point thereon to the ends thereof.

Claim 53

A clock synchronizing apparatus as defined in claim 8, further including means at each said application module for compensating for non-planar electromagnetic wave fronts.

Claim 54

A clock synchronizing apparatus as defined in claim 8, said detecting means including radio antennas, optical, infra-red photodiodes, and/or lens assemblies.

Claim 55

An electronic system comprising: a signal source for providing an initial signal; a plurality of receivers, each having a first and second input lead, each of said receivers requiring the use of an associated one of a plurality of locally generated signals, each of said plurality of locally generated signals corresponding to said initial signal and delayed from said initial signal by a a signal path having an end for receiving said initial signal, each of said first input leads of said plurality of receivers being connected to said signal path at an associated one of a first plurality of locations along said signal path such that each of said receivers has an associated first propagation delay between said source and said location, such that said first propagation delays are not equal, and each of said second input leads of said plurality of receivers being connected to said signal path at an associated one of a second plurality of locations along said signal path such that each of said receivers has an associated second propagation delay between said source and said location, such that said second propagation delays are not equal; and a plurality of means, each association with one of said receivers for combining said signals on said first and second input leads in order to generate a locally generated signal corresponding to said initial signal and having a propagation delay from said initial signal which is equal to the average of said first propagation delay and said second propagation delay associated with said receiver.

Claim 56

An electronic system comprising: a signal source for providing an initial signal; a plurality of receivers, each having a first and second input lead, each of said receivers requiring the use of an associated one of a plurality of locally generated signals, each of said plurality of locally generated signals corresponding to said initial signal and delayed from said initial signal by a a signal path having an end for receiving said initial signal, each of said first input leads of said plurality of receivers being connected to said signal path at an associated one of a first plurality of locations along said signal path such that each of said receivers has an associated first propagation delay between said source and said location, such that said first propagation delays are not equal, and each of said second input leads of said plurality of receivers being connected to said signal path at an associated one of a second plurality of locations along said signal path such that each of said receivers has an associated second propagation delay between said source and said location, such that said second propagation delays are not equal; and a plurality of means, each association with one of said receivers for combining said signals on said first and second input leads in order to generate a locally generated signal corresponding to said initial signal and having a propagation delay from said initial signal which is equal to the average of said first propagation delay and said second propagation delay associated with said receiver.

Claim 57

A system as in claim 52 wherein, for each receiver, the sum of the distances between said source and said first and second associated with said receivers is substantially equal to such sum associated with each other receiver.

Claim 58

Apparatus for providing a signal comprising: a first input lead for receiving a first signal corresponding to an initial signal and delayed from said initial signal by a first propagation delay; a second input lead for receiving a second input signal corresponding to said initial signal and delayed from said initial signal by a second propagation delay; an output lead for providing a locally generated signal corresponding to said initial signal and delayed from said initial signal by a third propagation delay which is a function of said first and second propagation delays; a first phase detector for providing a first phase comparison signal indicative of the phase relationship between said first input signal and said locally generated signal; a second phase detector for providing a second phase comparison signal indicative of the phase relationship between said second input signal and said locally generated signal; means for combining said phase comparison signal to provide a combined phase comparison signal; and a voltage controlled oscillator for providing said locally generated signal in response to said combined comparison signal.

Claim 59

Apparatus for providing a signal comprising: a first input lead for receiving a first signal corresponding to an initial signal and delayed from said initial signal by a first propagation delay; a second input lead for receiving a second input signal corresponding to said initial signal and delayed from said initial signal by a second propagation delay; an output lead for providing a locally generated signal corresponding to said initial signal and delayed from said initial signal by a third propagation delay which is a function of said first and second propagation delays; a first phase detector for providing a first phase comparison signal indicative of the phase relationship between said first input signal and said locally generated signal; a second phase detector for providing a second phase comparison signal indicative of the phase relationship between said second input signal and said locally generated signal; means for combining said phase comparison signal to provide a combined phase comparison signal; and a voltage controlled oscillator for providing said locally generated signal in response to said combined comparison signal.