US5361078A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple screen graphics display
Assignee: Nadimelia Ltd
•
Filing: 1990-11-09
•
Granted: 1994-11-01
•
Expires: 2010-11-09
Abstract
Abstract A display system comprises a wall of video screens each driven by a respective video driver (24A-24D). Information to be displayed is supplied from a host computer (10) having conventional input/output devices (12,14). Each circuit board of the host computer serves a number of video channels and supplies the information to be displayed on each screen to an associated portion of random access memory (22A to 22E). Thus, each screen displays a portion of an image or the whole image when the video drivers read out data in parallel from the portions of memory (22A to 22E). The information displayed may be altered via the input devices (12, 14) to the host computer (10).
Inventors
- 👤 Lester S. Caine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:57
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G06F3/1423; G06F3/1446; H; H04; H04N; H04N9/00; H04N9/12; G09; G09G; G09G2300/00; G09G2300/02; G09G2300/026; G09G2360/00; G09G2360/04
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
160 words
A display system comprising a host computer having a computer bus connected to a status register and to one input of a multiplexer, a coprocessor being connected to another input of the multiplexer, a random access memory mapped into a plurality of memory slots addressable by the host computer and each corresponding to a channel for a respective screen, each channel including a screen driver connected to the memory and operative to provide a video signal to the corresponding screen, wherein the host computer is capable of writing image data into any selected one of the memory slots and the screen drivers read image data out of the memory slots in parallel to provide simultaneous video signals for display on corresponding screens, wherein the multiplexer is controlled from the status register to select which of the host computer and coprocessor accessed the memory, and wherein the resolution of each screen is independent of the number of screen comprising the display.
Claim 2
Dependent Claim
160 words
A display system comprising a host computer having a computer bus connected to a status register and to one input of a multiplexer, a coprocessor being connected to another input of the multiplexer, a random access memory mapped into a plurality of memory slots addressable by the host computer and each corresponding to a channel for a respective screen, each channel including a screen driver connected to the memory and operative to provide a video signal to the corresponding screen, wherein the host computer is capable of writing image data into any selected one of the memory slots and the screen drivers read image data out of the memory slots in parallel to provide simultaneous video signals for display on corresponding screens, wherein the multiplexer is controlled from the status register to select which of the host computer and coprocessor accessed the memory, and wherein the resolution of each screen is independent of the number of screen comprising the display.
Claim 3
Dependent Claim
21 words
A display system according to claim 1, wherein the host computer and the screen drivers access the memory in time-multiplexed manner.
Claim 4
Dependent Claim
24 words
A display system according to claim 2, wherein the time multiplexing is controlled by a synchronising generator independently of the host computer clock cycle.
Claim 5
Dependent Claim
42 words
A display system according to claim 1, wherein each memory slot includes a plurality of image pages and wherein the host computer has a computer bus connected to a status register storing data determining which page is displayed via each image driver.
References Cited (Backward Citations)
GB1193546A
Cited
GB1326103A
Cited
GB1304473A
Cited
GB1353131A
Cited
GB1370852A
Cited
GB1486678A
Cited
US3961324A
Cited
US4057849A
Cited
GB1470785A
Cited
GB2100098A
Cited
EP0074696A1
Cited
US4760388A
Cited
GB2123656A
Cited
US4761641A
Cited
GB2148007A
Cited
EP0222920A1
Cited
US4704697A
Cited
EP0230241A1
Cited
US4800376A
Cited
EP0250123A1
Cited
WO1988000751A2
Cited
GB2205470A
Cited
US4884068A
Cited
WO1988010052A1
Cited
US4866530A
Cited
EP0331847A2
Cited
US4965559A
Cited
EP0351825A2
Cited
EP0376332A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |