Push-pull amplifier

Claim 2

An amplifier circuit comprising: an input differential amplifier stage, for receiving an input signal, and for providing an intermediate amplified signal in response to said input signal; an output stage comprising a pair of output transistors, each of said transistors having a gate electrode, a drain electrode, and a source electrode, and a quiescent current associated therewith, wherein the source electrode of an upper one of said pair of output transistors is coupled to the drain electrode of a lower one of said pair of output transistors, and wherein an amplifier output signal, responsive to said intermediate amplified signal, is provided at the source electrode of said upper one of said pair of output transistors; and a driver stage, coupled between said input differential amplifier stage and said output stage, comprising a first driver portion having a first drive transistor for providing a gate signal to the gate electrode of said upper one of said pair of output transistors and a second driver portion having a second drive transistor for providing a gate signal to the gate electrode of said lower one of said pair of output transistors, wherein each of said first driver portion and said second driver portion comprises a replicating device having a current therethrough and having electrical characteristics substantially similar to the corresponding one of the pair of output transistors so that said quiescent current through each of the output transistors is proportional to said current through the corresponding replicating device.

Claim 3

The amplifier circuit recited in claim 1 wherein the replicating device of said first driver portion is coupled to said intermediate amplified signal.

Claim 4

The amplifier circuit recited in claim 2 wherein each of said replicating devices of said first and second driver portions is a MOS transistor having interconnected drain and gate electrodes.

Claim 5

The amplifier circuit recited in claim 3 wherein each of said first driver portion and said second driver portion comprises a buffer amplifier fed by said intermediate amplified signal for providing a buffer signal to the gate electrode of the corresponding one of the pair of output transistors.

Claim 6

The amplifier circuit recited in claim 4 wherein each of said first driver portion and said second driver portion further comprises a summing circuit for summing the voltage across the corresponding one of the replicating devices with the buffer signal of the corresponding one of the buffer amplifiers to provide said gate signals.

Claim 7

An amplifier circuit comprising: an input differential amplifier stage, for receiving an input signal, and for providing an intermediate amplified signal in response to said input signal; an output stage comprising a pair of output transistors, each of said transistors having a gate electrode, a drain electrode, and a source electrode, and a quiescent current associated therewith, wherein the source electrode of an upper one of said pair of output transistors is coupled to the drain electrode of a lower one of said pair of output transistors, and wherein an amplifier output signal, responsive to said intermediate amplified signal, is provided at the source electrode of said upper one of said pair of output transistors; a driver stage, coupled between said input differential amplifier stage and said output stage, comprising a first driver portion having a first drive transistor for providing a gate signal to the gate electrode of said upper one of said pair of output transistors and a second driver portion having a second drive transistor for providing a gate signal to the gate electrode of said lower one of said pair of output transistors, wherein each of said first driver portion and said second driver portion comprises a replicating device having a current therethrough and having electrical characteristics substantially similar to the corresponding one of the pair of output transistors so that said quiescent current through each of the output transistors is proportional to said current through the corresponding replicating device; and a cross current feedback circuit for regulating the quiescent current flow through each of said pair of output transistors, said cross current circuit comprising a sensor for sensing a current flow through said lower output transistor and a circuit, coupled to said first drive transistor, for adjusting the gate signal provided by said first drive transistor to the gate electrode of the upper output transistor in response to the sensed current flow through the lower output transistor.

Claim 8

An amplifier circuit comprising: an input differential amplifier stage, for receiving an input signal, and for providing an intermediate amplified signal in response to said input signal; an output stage comprising a pair of output transistors, each of said transistors having a gate electrode, a drain electrode, and a source electrode, and a quiescent current associated therewith, wherein the source electrode of an upper one of said pair of output transistors is coupled to the drain electrode of a lower one of said pair of output transistors, and wherein an amplifier output signal, responsive to said intermediate amplified signal, is provided at the source electrode of said upper one of said pair of output transistors; a driver stage, coupled between said input differential amplifier stage and said output stage, comprising a first driver portion having a first drive transistor for providing a gate signal to the gate electrode of said upper one of said pair of output transistors and a second driver portion having a second drive transistor for providing a gate signal to the gate electrode of said lower one of said pair of output transistors, wherein each of said first driver portion and said second driver portion comprises a replicating device having a current therethrough and having electrical characteristics substantially similar to the corresponding one of the pair of output transistors so that said quiescent current through each of the output transistors is proportional to said current through the corresponding replicating device; and a cross current feedback circuit for regulating the quiescent current flow through each of said pair of output transistors, said cross current circuit comprising a sensor for sensing a current flow through said lower output transistor and a circuit, coupled to said first drive transistor, for adjusting the gate signal provided by said first drive transistor to the gate electrode of the upper output transistor in response to the sensed current flow through the lower output transistor.

Claim 9

A driver circuit for driving a source follower output transistor of a push-pull amplifier, said transistor being coupled to a positive supply voltage, said amplifier having an input stage for receiving an input signal and for providing an intermediate amplified signal, and an output stage, including said source follower output transistor, for providing an amplifier output signal in response to said input signal, said driver circuit comprising: a replicating transistor having electrical characteristics substantially similar to those of said source follower output transistor; a buffer amplifier having a first input coupled to said intermediate amplified signal, a second input coupled to said amplifier output signal, and an output providing a buffer signal; and a summing circuit, coupled to said output of said buffer amplifier and said replicating transistor, for summing the voltage across said replicating transistor with said buffer signal to provide a gate signal to a gate electrode of said source follower output transistor.

Claim 10

A driver circuit for driving a source follower output transistor of a push-pull amplifier, said transistor being coupled to a positive supply voltage, said amplifier having an input stage for receiving an input signal and for providing an intermediate amplified signal, and an output stage, including said source follower output transistor, for providing an amplifier output signal in response to said input signal, said driver circuit comprising: a replicating transistor having electrical characteristics substantially similar to those of said source follower output transistor; a buffer amplifier having a first input coupled to said intermediate amplified signal, a second input coupled to said amplifier output signal, and an output providing a buffer signal; and a summing circuit, coupled to said output of said buffer amplifier and said replicating transistor, for summing the voltage across said replicating transistor with said buffer signal to provide a gate signal to a gate electrode of said source follower output transistor.

Claim 11

The driver circuit recited in claim 7 wherein said replicating transistor has a drain electrode, a gate electrode, and a source electrode and wherein said drain electrode and said gate electrode are interconnected and said summing circuit is coupled to said drain electrode of said replicating transistor.

Claim 12

The driver circuit recited in claim 8 wherein said source electrode of said replicating transistor is coupled to said intermediate amplified signal.

Claim 13

An amplifier circuit comprising: an input differential amplifier stage, for receiving an input signal, and for providing an intermediate amplified signal in response to said input signal; a pair of NMOS output transistors, each of said transistors having a gate electrode, a drain electrode, and a source electrode, and a quiescent current associated therewith, wherein the source electrode of an upper one of said pair of output transistors is coupled to the drain electrode of a lower one of said pair of output transistors, and wherein an amplifier output signal, responsive to said intermediate amplified signal, is provided at the source electrode of said upper one of said pair of transistors; a driver stage, coupled between said input differential amplifier stage and said output stage, comprising a first driver portion having a first drive transistor for providing a gate signal to the gate electrode of said upper one of said pair of output transistors and a second driver portion having a second drive transistor for providing a gate signal to the gate electrode of said lower one of said pair of output transistors, wherein each of said first driver portion and said second driver portion comprises a replicating device having a current therethrough and having electrical characteristics substantially similar to the corresponding one of the pair of output transistors so that said quiescent current through each of the output transistors is proportional to said current through the corresponding replicating device; and a cross current feedback circuit comprising: (a) a sensor for sensing a current flow through said lower output transistor; and (b) a circuit, coupled to said first drive transistor, for adjusting the gate signal provided to the gate electrode of the upper output transistor in response to the sensed current flow through the lower output transistor.

Claim 14

An amplifier circuit comprising: an input differential amplifier stage, for receiving an input signal, and for providing an intermediate amplified signal in response to said input signal; a pair of NMOS output transistors, each of said transistors having a gate electrode, a drain electrode, and a source electrode, and a quiescent current associated therewith, wherein the source electrode of an upper one of said pair of output transistors is coupled to the drain electrode of a lower one of said pair of output transistors, and wherein an amplifier output signal, responsive to said intermediate amplified signal, is provided at the source electrode of said upper one of said pair of transistors; a driver stage, coupled between said input differential amplifier stage and said output stage, comprising a first driver portion having a first drive transistor for providing a gate signal to the gate electrode of said upper one of said pair of output transistors and a second driver portion having a second drive transistor for providing a gate signal to the gate electrode of said lower one of said pair of output transistors, wherein each of said first driver portion and said second driver portion comprises a replicating device having a current therethrough and having electrical characteristics substantially similar to the corresponding one of the pair of output transistors so that said quiescent current through each of the output transistors is proportional to said current through the corresponding replicating device; and a cross current feedback circuit comprising: (a) a sensor for sensing a current flow through said lower output transistor; and (b) a circuit, coupled to said first drive transistor, for adjusting the gate signal provided to the gate electrode of the upper output transistor in response to the sensed current flow through the lower output transistor.

Claim 15

The amplifier circuit recited in claim 10 wherein said sensor comprises a sense transistor having a gate electrode coupled to the gate electrode of said lower output transistor, wherein said sense transistor conducts a current proportional to said current flow through said lower output transistor.

Claim 16

The amplifier circuit recited in claim 11 wherein the replicating device of said first driver portion is coupled to said intermediate amplified signal.

Claim 17

The amplifier circuit recited in claim 10 wherein each of said replicating devices of said first and second driver portions is a MOS transistor having interconnected drain and gate electrodes.

Claim 18

A driver circuit for driving a source follower output transistor of a push-pull amplifier, said transistor being coupled to a positive supply voltage, said amplifier having an input stage for receiving an input signal and for providing an intermediate amplified signal, and an output stage, including said source follower output transistor, for providing an amplifier output signal in response to said input signal, said driver circuit comprising: a replicating device having electrical characteristics substantially similar to those of said source follower output transistor; a buffer amplifier having a first input coupled to said intermediate amplified signal, a second input coupled to said amplifier output signal, and an output providing a buffer signal; and a summing circuit, coupled to said output of said buffer amplifier and said replicating transistor, for summing the voltage across said replicating device with said buffer signal to provide a gate signal to a gate electrode of said source follower output transistor.

Claim 19

A driver circuit for driving a source follower output transistor of a push-pull amplifier, said transistor being coupled to a positive supply voltage, said amplifier having an input stage for receiving an input signal and for providing an intermediate amplified signal, and an output stage, including said source follower output transistor, for providing an amplifier output signal in response to said input signal, said driver circuit comprising: a replicating device having electrical characteristics substantially similar to those of said source follower output transistor; a buffer amplifier having a first input coupled to said intermediate amplified signal, a second input coupled to said amplifier output signal, and an output providing a buffer signal; and a summing circuit, coupled to said output of said buffer amplifier and said replicating transistor, for summing the voltage across said replicating device with said buffer signal to provide a gate signal to a gate electrode of said source follower output transistor.

Claim 20

The driver circuit recited in claim 14 wherein said replicating device is a MOS transistor having a drain electrode, a gate electrode, and a source electrode, wherein said drain and gate electrodes are interconnected.

Claim 21

The driver circuit recited in claim 15 wherein said source electrode of said replicating device is coupled to said intermediate amplified signal.

Claim 22

An amplifier circuit comprising: an input differential amplifier stage for providing an intermediate amplified signal in response to an input signal; an output stage comprising a pair of output transistors, each of said transistors having a gate electrode, a drain electrode, and a source electrode, and a quiescent current associated therewith, wherein the source electrode of an upper one of said pair of output transistors is coupled to the drain electrode of a lower one of said pair of output transistors, and wherein an amplifier output signal, responsive to said intermediate amplified signal, is provided at the source electrode of said upper one of said pair of output transistors; and a driver stage, coupled between said input differential amplifier stage and said output stage, comprising a first driver portion for providing a gate signal to the gate electrode of said upper one of said pair of output transistors and a second driver portion for providing a gate signal to the gate electrode of said lower one of said pair of output transistors, wherein each of said first driver portion and said second driver portion comprises a replicating transistor having a current therethrough and having electrical characteristics substantially similar to the corresponding one of the pair of output transistors so that said quiescent current and said current through the corresponding replicating transistor are related by the ratio of the gate size of the output transistor to the gate size of the corresponding replicating transistor.

Claim 23

An amplifier circuit comprising: an input differential amplifier stage for providing an intermediate amplified signal in response to an input signal; an output stage comprising a pair of output transistors, each of said transistors having a gate electrode, a drain electrode, and a source electrode, and a quiescent current associated therewith, wherein the source electrode of an upper one of said pair of output transistors is coupled to the drain electrode of a lower one of said pair of output transistors, and wherein an amplifier output signal, responsive to said intermediate amplified signal, is provided at the source electrode of said upper one of said pair of output transistors; and a driver stage, coupled between said input differential amplifier stage and said output stage, comprising a first driver portion for providing a gate signal to the gate electrode of said upper one of said pair of output transistors and a second driver portion for providing a gate signal to the gate electrode of said lower one of said pair of output transistors, wherein each of said first driver portion and said second driver portion comprises a replicating transistor having a current therethrough and having electrical characteristics substantially similar to the corresponding one of the pair of output transistors so that said quiescent current and said current through the corresponding replicating transistor are related by the ratio of the gate size of the output transistor to the gate size of the corresponding replicating transistor.

Claim 24

An amplifier circuit comprising: an input differential amplifier stage, for receiving an input signal, and for providing an intermediate amplified signal in response to said input signal; an output stage comprising a pair of output transistors, each of said output transistors having a gate electrode, a drain electrode, and a source electrode, wherein the source electrode of an upper one of said pair of output transistors is coupled to the drain electrode of a lower one of said pair of output transistors, and wherein an amplifier output signal, responsive to said intermediate amplified signal, is provided at the source electrode of said upper one of said pair of output transistors; a driver stage, coupled between said input differential amplifier stage and said output stage, comprising a first driver portion having a first drive transistor for providing a gate signal to the gate electrode of said upper one of said pair of output transistors and a second driver portion having a second drive transistor for providing a gate signal to the gate electrode of said lower one of said pair of output transistors, wherein each of said first driver portion and said second driver portion comprises a replicating device having electrical characteristics substantially similar to the corresponding one of the pair of output transistors and wherein said gate signals are related to the voltage across the corresponding replicating device and wherein the replicating device of said first driver portion is coupled to said intermediate amplified signal and wherein each of said replicating devices of said first and second driver portions is a MOS transistor having an interconnected drain and gate electrodes, each of said first driver portion and said second driver portion further comprising: (a) a buffer amplifier fed by said intermediate amplified signal for providing a buffer signal to the gate electrode of the corresponding one of the pair of output transistors; and (b) a summing circuit for summing the voltage across the corresponding one of the replicating devices with the buffer signal of the corresponding one of the buffer amplifiers to provide said gate signals; and a cross current feedback circuit for regulating the quiescent current flow through each of said pair of output transistors, said cross current circuit comprising a sensor for sensing the current flow through said lower output transistor and a circuit, coupled to said first drive transistor for adjusting the gate signal provided by said first drive transistor to the gate electrode of the upper output transistor in response to the sensed current flow through the lower transistor.

Claim 25

An amplifier circuit comprising: an input differential amplifier stage, for receiving an input signal, and for providing an intermediate amplified signal in response to said input signal; an output stage comprising a pair of output transistors, each of said output transistors having a gate electrode, a drain electrode, and a source electrode, wherein the source electrode of an upper one of said pair of output transistors is coupled to the drain electrode of a lower one of said pair of output transistors, and wherein an amplifier output signal, responsive to said intermediate amplified signal, is provided at the source electrode of said upper one of said pair of output transistors; a driver stage, coupled between said input differential amplifier stage and said output stage, comprising a first driver portion having a first drive transistor for providing a gate signal to the gate electrode of said upper one of said pair of output transistors and a second driver portion having a second drive transistor for providing a gate signal to the gate electrode of said lower one of said pair of output transistors, wherein each of said first driver portion and said second driver portion comprises a replicating device having electrical characteristics substantially similar to the corresponding one of the pair of output transistors and wherein said gate signals are related to the voltage across the corresponding replicating device and wherein the replicating device of said first driver portion is coupled to said intermediate amplified signal and wherein each of said replicating devices of said first and second driver portions is a MOS transistor having an interconnected drain and gate electrodes, each of said first driver portion and said second driver portion further comprising: (a) a buffer amplifier fed by said intermediate amplified signal for providing a buffer signal to the gate electrode of the corresponding one of the pair of output transistors; and (b) a summing circuit for summing the voltage across the corresponding one of the replicating devices with the buffer signal of the corresponding one of the buffer amplifiers to provide said gate signals; and a cross current feedback circuit for regulating the quiescent current flow through each of said pair of output transistors, said cross current circuit comprising a sensor for sensing the current flow through said lower output transistor and a circuit, coupled to said first drive transistor for adjusting the gate signal provided by said first drive transistor to the gate electrode of the upper output transistor in response to the sensed current flow through the lower transistor.