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US5359624A
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System and method for chip timing synchronization in an adaptive direct sequence CDMA communication system
Assignee: Motorola Solutions Inc
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Filing: 1993-06-07
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Granted: 1994-10-25
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Expires: 2013-06-07
Abstract
Abstract In a CDMA communication system (100) capable of communicating between a receiver (10) and a transmitter (20)direct sequence spread spectrum communication signals (30), a system and method for synchronizing receiver chip timing and transmitter chip timing. Transmitter (10) transmits a training bit sequence (31) coded with a spreading chip sequence. The receiver (20) adaptively determines a representation of a despreading chip sequence using a tapped delay line equalizer (400). The representation of the despreading chip sequence is represented by tap coefficient potentials of the equalizer (400). Receiver chip timing offset is determined based on the tap coefficient potentials.
Inventors
- 👤 Edward K. B. Lee
- 👤 Jimmy Cadd
- 👤 Tracy L. Fulghum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:46
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/707; H04B1/7097
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
120 words
In a direct sequence CDMA spread spectrum communication system, wherein spread spectrum communication signals comprising binary bits coded with spreading chip sequences are communicated between a transmitter and a receiver; a chip synchronization method for synchronizing receiver chip timing with transmitter chip timing comprising the steps of: a) transmitting a direct sequence spread spectrum communication signal including a redundant training bit sequence; b) receiving said predetermined redundant training bit sequence; c) adaptively determining a representation of a desk, reading chip sequence based on said redundant training bit sequence using a tapped delay line equalizer; said despreading chip sequence being represented by tap coefficient potentials of said equalizer; and d) determining receiver chip timing offset based on said tap coefficient potentials.
Claim 2
Dependent Claim
120 words
In a direct sequence CDMA spread spectrum communication system, wherein spread spectrum communication signals comprising binary bits coded with spreading chip sequences are communicated between a transmitter and a receiver; a chip synchronization method for synchronizing receiver chip timing with transmitter chip timing comprising the steps of: a) transmitting a direct sequence spread spectrum communication signal including a redundant training bit sequence; b) receiving said predetermined redundant training bit sequence; c) adaptively determining a representation of a desk, reading chip sequence based on said redundant training bit sequence using a tapped delay line equalizer; said despreading chip sequence being represented by tap coefficient potentials of said equalizer; and d) determining receiver chip timing offset based on said tap coefficient potentials.
Claim 3
Dependent Claim
32 words
The method of claim 1, wherein said step of determining the receiver chip timing offset includes the step of determining a ratio of minimum tap coefficient potential to maximum tap coefficient potential.
Claim 4
Dependent Claim
35 words
The method of claim 1, further including the step of determining the sign of the chip receiver timing offset based on the polarity of at least one of the tap coefficients after a chip transition.
Claim 5
Dependent Claim
94 words
In a CDMA receiver capable of receiving spread spectrum communication signals comprising binary bits coded with spreading chip sequences form a transmitter; a bit synchronization method for synchronizing receiver chip timing with transmitter chip timing comprising the steps off a) receiving a redundant training bit sequence; b) adaptively determining a representation of a despreading chip sequence based on said redundant training bit sequence using a tapped delay line equalizer, said despreading chip sequence being represented by tap coefficient potentials of said equalizer; c) determining receiver chip timing offset based on said tap coefficient potentials.
Claim 6
Dependent Claim
94 words
In a CDMA receiver capable of receiving spread spectrum communication signals comprising binary bits coded with spreading chip sequences form a transmitter; a bit synchronization method for synchronizing receiver chip timing with transmitter chip timing comprising the steps off a) receiving a redundant training bit sequence; b) adaptively determining a representation of a despreading chip sequence based on said redundant training bit sequence using a tapped delay line equalizer, said despreading chip sequence being represented by tap coefficient potentials of said equalizer; c) determining receiver chip timing offset based on said tap coefficient potentials.
Claim 7
Dependent Claim
30 words
The method of claim 4, wherein said step of determining the receiver chip timing offset includes the step of determining a ratio of minimum coefficient potential to maximum coefficient potential.
Claim 8
Dependent Claim
34 words
The method of claim 4, further including the step of determining the sign of the chip timing offset based on the polarity of at least one of the tap coefficients after a chip transition.
Claim 9
Dependent Claim
79 words
A CDMA communication system for communicating direct sequence spread spectrum communication signals comprising: a transmitter for transmitting a direct sequence spread spectrum communication signal including a redundant training bit sequence; a receiver for receiving said direct sequence spread spectrum communication signal including: a tapped delay line equalizer for adaptively providing tap coefficient potentials representing a despreading chip sequence based on said redundant training bit sequence; determination means for determining receiver chip timing offset based on said tap coefficient potentials.
Claim 10
Dependent Claim
79 words
A CDMA communication system for communicating direct sequence spread spectrum communication signals comprising: a transmitter for transmitting a direct sequence spread spectrum communication signal including a redundant training bit sequence; a receiver for receiving said direct sequence spread spectrum communication signal including: a tapped delay line equalizer for adaptively providing tap coefficient potentials representing a despreading chip sequence based on said redundant training bit sequence; determination means for determining receiver chip timing offset based on said tap coefficient potentials.
Claim 11
Dependent Claim
27 words
The CDMA communication system of claim 7, wherein said determination means includes means for determining a ratio of minimum tap coefficient potential to maximum tap coefficient potential.
Claim 12
Dependent Claim
35 words
The CDMA communication system of claim 7, further including means for determining the sign of the chip timing offset based on the polarity of at least one of the tap coefficients after a chip transition.
Claim 13
Dependent Claim
59 words
A direct sequence CDMA receiver, comprising: means for receiving a direct sequence spread spectrum communication signal including a redundant training bit sequence; a tapped delay line equalizer for adaptively providing tap coefficient potentials representing a despreading chip sequence based on said redundant training bit sequence; determination means for determining receiver chip timing offset based on said tap coefficient potentials.
Claim 14
Dependent Claim
59 words
A direct sequence CDMA receiver, comprising: means for receiving a direct sequence spread spectrum communication signal including a redundant training bit sequence; a tapped delay line equalizer for adaptively providing tap coefficient potentials representing a despreading chip sequence based on said redundant training bit sequence; determination means for determining receiver chip timing offset based on said tap coefficient potentials.
Claim 15
Dependent Claim
25 words
The receiver of claim 10, wherein said determination means includes means for determining a ratio of minimum tap coefficient potential to maximum tap coefficient potential.
Claim 16
Dependent Claim
33 words
The receiver of claim 10, further including means for determining the sign of the chip timing offset based on the polarity of at least one of the tap coefficients after a chip transition.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-24 | 1998-04-25 | 1998-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-24 | 2002-04-25 | 2002-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-24 | 2006-04-25 | 2006-10-25 | $7700.00 | Window Closed / Lapsed |