Semiconductor memory device having improved redundancy efficiency

Claim 2

A row redundancy circuit in a semiconductor memory device including a first memory cell array having a first redundant memory cell array for replacing a defective memory cell, a second memory cell array, adjacent to said first memory cell array, having a second redundant memory cell array for replacing a defective memory cell, and sense amplifier between said first and second memory cell arrays for sensing data from said first and second memory cell arrays, the row redundancy circuit comprising: fuse box means, receiving block selection address signals, for selecting the redundant memory cell arrays, receiving row address signals, for selecting redundant word lines in the selected redundant memory cell array, and, for producing an output, said fuse box means comprising at least one fuse on a signal path used to receive said block selection address signals; and redundant word line driver means, receiving the output of said fuse box means, for supplying redundant word line driving signals to said first and second redundant memory cell arrays respectively.

Claim 3

A row redundancy circuit as claimed in claim 1, wherein said redundant word line driver means can repair the defective memory cells both in the first and second memory cell arrays.

Claim 4

A row redundancy circuit as claimed in claim 1, wherein said fuse box means comprises: means for receiving the row address signal for selecting redundant word lines in the selected redundant memory cell array; first and second MOS transistors each receiving first and second block selection address signals; first and second fuses respectively connected between the output of said fuse box means and said first and second MOS transistors; and a third MOS transistor receiving a third block selection address signal, connected between the output of said fuse box means and a ground reference voltage.

Claim 5

A row redundancy circuit used for a semiconductor memory device including first and second memory cell arrays being adjacent to each other, and first and second sense amplifiers respectively connected to said first and second memory cell arrays for sensing data from said first and second memory cell arrays, comprising: first and second redundant memory cell arrays respectively subjected to said first and second memory cell arrays, said first and second redundant memory cell arrays each being divided again into first and second redundant memory cell array blocks; a first fuse box receiving block selection address signals for selecting the redundant memory cell arrays and row address signals for selecting redundant word lines in the selected redundant memory cell array, said first fuse box comprising fuses on a path of receiving said block selection address signals; a first redundant word line driver receiving the output of said first fuse box, for supplying a redundant word line driving signal to said first redundant memory cell array blocks of the respective first and second redundant memory cell arrays; a second fuse box receiving the block selection address signals for selecting the redundant memory cell arrays and the row address signals for selecting redundant word lines in the selected redundant memory cell array, said second fuse box comprising fuses on a path of receiving said block selection address signals; and a second redundant word line driver receiving the output of said second fuse box, for supplying a redundant word line driving signal to said second redundant memory cell array blocks of the respective first and second redundant memory cell arrays; whereby said first and second redundant word line drivers each can repair the defective memory cells both in the first and second memory cell arrays, respectively.

Claim 6

A row redundancy circuit used for a semiconductor memory device including first and second memory cell arrays being adjacent to each other, and first and second sense amplifiers respectively connected to said first and second memory cell arrays for sensing data from said first and second memory cell arrays, comprising: first and second redundant memory cell arrays respectively subjected to said first and second memory cell arrays, said first and second redundant memory cell arrays each being divided again into first and second redundant memory cell array blocks; a first fuse box receiving block selection address signals for selecting the redundant memory cell arrays and row address signals for selecting redundant word lines in the selected redundant memory cell array, said first fuse box comprising fuses on a path of receiving said block selection address signals; a first redundant word line driver receiving the output of said first fuse box, for supplying a redundant word line driving signal to said first redundant memory cell array blocks of the respective first and second redundant memory cell arrays; a second fuse box receiving the block selection address signals for selecting the redundant memory cell arrays and the row address signals for selecting redundant word lines in the selected redundant memory cell array, said second fuse box comprising fuses on a path of receiving said block selection address signals; and a second redundant word line driver receiving the output of said second fuse box, for supplying a redundant word line driving signal to said second redundant memory cell array blocks of the respective first and second redundant memory cell arrays; whereby said first and second redundant word line drivers each can repair the defective memory cells both in the first and second memory cell arrays, respectively.

Claim 7

A row redundancy circuit as claimed in claim 4, wherein said first and second fuse boxes each comprise: means for receiving the row address signal for selecting redundant word lines in the selected redundant memory cell array; first and second MOS transistors each receiving first and second block selection address signals; first and second fuses respectively connected between the output of the respective first and second fuse boxes and said first and second MOS transistors; and a third MOS transistor receiving a third block selection address signal, connected between the output of the respective first and second fuse boxes and a ground reference voltage.