Flash eeprom array with improved high endurance

Claim 2

In a semiconductor integrated circuit memory device having an over-erased bit correction structure for performing a correction operation on over-erased memory cells in the memory device, said correction structure comprising, in combination: a cell matrix (12) having a plurality of memory cells arrayed in rows of word lines and columns of bit lines intersecting said rows of word lines, each of said memory cells including a floating gate array transistor having its gate connected to one of said rows of word lines, its drain connected to one of said columns of bit lines, and its source connected to a ground potential; row decoder means (14) responsive to row address signals and being operatively connected to said cell matrix for selecting one of said rows of word lines; column decoder means (16) responsive to column address signals and being operatively connected to said cell matrix for selecting one of said columns of bit lines; reference periphery bit line circuit means (42) for generating a reference current for said columns of bit lines; sensing circuit means (20) for comparing leakage current in a selected one of said columns of bit lines and the reference current associated with the selected one of said columns of bit lines during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell, said logic signal being at a high logic level when said bit line leakage current is greater than said reference current indicative of an over-erased memory cell and being at a low logic level when said bit line leakage current is less than said reference current indicative of a properly programmed memory cell; data input buffer circuit means (26) for comparing said logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal which is at a high logic level when said logic signal and said data signal are equal; pulse counter means (30) coupled to said data input buffer circuit means for counting a plurality of programming pulses applied thereto; and said data input circuit means selectively connecting only certain ones of said columns of bit lines to said pulse counter means in which said bit match signal is at the high logic level so as to program back over-erased memory cells connected to only the certain ones of said columns of bit lines.

Claim 3

In a semiconductor integrated circuit memory device as claimed in claim 1, wherein said plurality of programming pulses serve to change the negative threshold of the array transistor in the over-erased memory cell to a positive threshold voltage.

Claim 4

In a semiconductor integrated circuit memory device as claimed in claim 1, wherein said sensing circuit means is comprised of sense ratio resistive network (38) operatively connected to said columns of bit lines for generating a first resistance value corresponding to the leakage current in the selected one of said columns of bit lines, reference resistive network means (36) operatively connected to said reference periphery bit line circuit means for generating a second resistance value corresponding to the reference current, and comparator means (34) having a first input coupled to a sense ratio resistive network means and a second input connected to said reference resistive network means for comparing the column leakage current and the reference current.

Claim 5

In a semiconductor integrated circuit memory device as claimed in claim 3, wherein the ratio of said first resistance value to said second resistance value is defined to be a sense ratio which is increased to approximately 12:1 during the APDE mode of operation so as to enhance the endurance of the memory device.

Claim 6

In a semiconductor integrated circuit memory device as claimed in claim 1, wherein said reference periphery bit line circuit means is comprised of a mini-array for generating a corresponding reference current for each output line.

Claim 7

In a semiconductor integrated circuit memory device as claimed in claim 5, wherein said reference periphery bit line circuit means includes means (302) for doubling the sense ratio of said sensing circuit means.

Claim 8

In a semiconductor integrated circuit memory device as claimed in claim 1, further comprising match circuit means (33) responsive to the bit match signal from eight data input buffer means for generating a byte match signal which is at a high logic level only when each match signal is high.

Claim 9

In a semiconductor integrated circuit memory device as claimed in claim 7, wherein said pulse counter means terminates said plurality of pulses only when the byte match signal is at a high logic level indicating that a complete match exists between the byte data from the array and the byte data to be programmed.

Claim 10

In a semiconductor integrated circuit memory device as claimed in claim 8, further including means (28) responsive to said byte match circuit for selecting the next byte in the array to be programmed.

Claim 11

In a semiconductor integrated circuit memory device having an over-erased bit correction structure for performing a correction operation on over-erased memory cells in the memory device, said correction structure comprising, in combination: a cell matrix (12) having a plurality of memory cells arrayed in rows of word lines and columns of bit lines intersecting said rows of word lines, each of said memory cells including a floating gate array transistor having its gate connected to one of said rows of word lines, its drain connected to one of said columns of bit lines, and its source connected to a ground potential; row decoder means (14) responsive to row address signals and being operatively connected to said cell matrix for selecting one of said rows of word lines; column decoder means (16) responsive to column address signals and being operatively connected to said cell matrix for selecting one of said columns of bit lines; reference periphery bit line circuit means (44) for generating multiple reference currents each associated with one of the said columns of bit lines; sensing circuit means (20) for comparing leakage current in a selected one of said columns of bit lines and the reference current associated with the selected one of said columns of bit lines during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell, said logic signal being at a high logic level when said bit line leakage current is greater than said reference current indicative of an over-erased memory cell and being at a low logic level when said bit line leakage current is less than said reference current indicative of a properly programmed memory cell; data input buffer circuit means (26) for comparing said logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal which is at a high logic level when said logic signal and said data signal are equal; pulse counter means (30) coupled to said data input buffer circuit means for counting a plurality of programming pulses applied thereto; and said data input circuit means selectively connecting only certain ones of said columns of bit lines to said pulse counter means in which said bit match signal is at the high logic level so as to program back over-erased memory cells connected to only the certain ones of said columns of bit lines.

Claim 12

In a semiconductor integrated circuit memory device having an over-erased bit correction structure for performing a correction operation on over-erased memory cells in the memory device, said correction structure comprising, in combination: a cell matrix (12) having a plurality of memory cells arrayed in rows of word lines and columns of bit lines intersecting said rows of word lines, each of said memory cells including a floating gate array transistor having its gate connected to one of said rows of word lines, its drain connected to one of said columns of bit lines, and its source connected to a ground potential; row decoder means (14) responsive to row address signals and being operatively connected to said cell matrix for selecting one of said rows of word lines; column decoder means (16) responsive to column address signals and being operatively connected to said cell matrix for selecting one of said columns of bit lines; reference periphery bit line circuit means (44) for generating multiple reference currents each associated with one of the said columns of bit lines; sensing circuit means (20) for comparing leakage current in a selected one of said columns of bit lines and the reference current associated with the selected one of said columns of bit lines during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell, said logic signal being at a high logic level when said bit line leakage current is greater than said reference current indicative of an over-erased memory cell and being at a low logic level when said bit line leakage current is less than said reference current indicative of a properly programmed memory cell; data input buffer circuit means (26) for comparing said logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal which is at a high logic level when said logic signal and said data signal are equal; pulse counter means (30) coupled to said data input buffer circuit means for counting a plurality of programming pulses applied thereto; and said data input circuit means selectively connecting only certain ones of said columns of bit lines to said pulse counter means in which said bit match signal is at the high logic level so as to program back over-erased memory cells connected to only the certain ones of said columns of bit lines.

Claim 13

In a semiconductor integrated circuit memory device as claimed in claim 10, wherein said plurality of programming pulses serve to change the negative threshold of the array transistor in the over-erased memory cell to a positive threshold voltage.

Claim 14

In a semiconductor integrated circuit memory device as claimed in claim 10, wherein said sensing circuit means is comprised of sense ratio resistive network (38) operatively connected to said columns of bit lines for generating a first resistance value corresponding to the leakage current in the selected one of said columns of bit lines, reference resistive network means (36) operatively connected to said reference periphery bit line circuit means for generating a second resistance value corresponding to the reference current, and comparator means (34) having a first input coupled to a sense ratio resistive network means and a second input connected to said reference resistive network means for comparing the column leakage current and the reference current.

Claim 15

In a semiconductor integrated circuit memory device as claimed in claim 12, wherein the ratio of said first resistance value to said second resistance value is defined to be a sense ratio which is increased to approximately 12:1 during the APDE mode of operation so as to enhance the endurance of the memory device.

Claim 16

In a semiconductor integrated circuit memory device as claimed in claim 10, wherein said reference periphery bit line circuit means is comprised of a mini-array for generating the multiple reference currents for each output line.

Claim 17

In a semiconductor integrated circuit memory device as claimed in claim 14, wherein said reference periphery bit line circuit means includes means (302) for doubling the sense ratio of said sensing bit means.

Claim 18

In a semiconductor integrated circuit memory device as claimed in claim 10, further comprising match circuit means (33) responsive to the bit match signal from eight data input buffer means for generating a byte match signal which is at a high logic level only when each match signal is high.

Claim 19

In a semiconductor integrated circuit memory device as claimed in claim 16, wherein said pulse counter means terminates said plurality of pulses only when the byte match signal is at a high logic level indicating that a complete match exists between the byte data from the array and the byte data to be programmed.

Claim 20

In a semiconductor integrated circuit memory device as claimed in claim 17, further including means (28) responsive to said byte match circuit for selecting the next byte in the array to be programmed.

Claim 21

An over-erased bit correction for correcting over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as to render high endurance, said correction structure comprising: sensing circuit means (20) for comparing leakage current in a selected one of columns of bit lines and a reference current associated with the selected one of said columns of bit lines during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell, said logic signal being at a high logic level when said bit line leakage current is greater than said reference current indicative of an over-erased memory cell and being at a low logic level when said bit line leakage current is less than said reference current indicative of a properly programmed memory cell; data input buffer circuit means (26) for comparing said logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal which is at a high logic level when said logic signal and said data signal are equal; pulse counter means (30) coupled to said data input buffer circuit means for counting a plurality of programming pulses applied thereto; and said data input circuit means selectively connecting only certain ones of said columns of bit lines to said pulse counter means in which said bit match signal is at the high logic level so as to program back over-erased memory cells connected to only the certain ones of said columns of bit lines.

Claim 22

An over-erased bit correction for correcting over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as to render high endurance, said correction structure comprising: sensing circuit means (20) for comparing leakage current in a selected one of columns of bit lines and a reference current associated with the selected one of said columns of bit lines during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell, said logic signal being at a high logic level when said bit line leakage current is greater than said reference current indicative of an over-erased memory cell and being at a low logic level when said bit line leakage current is less than said reference current indicative of a properly programmed memory cell; data input buffer circuit means (26) for comparing said logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal which is at a high logic level when said logic signal and said data signal are equal; pulse counter means (30) coupled to said data input buffer circuit means for counting a plurality of programming pulses applied thereto; and said data input circuit means selectively connecting only certain ones of said columns of bit lines to said pulse counter means in which said bit match signal is at the high logic level so as to program back over-erased memory cells connected to only the certain ones of said columns of bit lines.

Claim 23

In a semiconductor integrated circuit memory device as claimed in claim 19, wherein said plurality of programming pulses serve to change the negative threshold of the array transistor in the over-erased memory cell to a positive threshold voltage.