Method for the erasure of memory cells, device designed to implement it, and use of said method in a device with non-supplied memory

Claim 1

A method for the erasure of EEPROM memory cells contained in a memory, said method consisting in: opening and initializing a counter in a random-access memory associated with an erasure control processor at the start of an operation for erasing a memory cell of said memory; said operation for erasing comprising erasure cycles, carrying out an erasure cycle on said memory cell, then a reading cycle for reading an actual status voltage of said memory cell and a comparison of the voltage read with an expected voltage corresponding to an erased state of said memory cell; when said read and expected voltages are different, triggering the iteration of the counter and a new erasure and reading cycle, then a comparison, for as long as the content of the counter remains smaller than a predetermined number, said predetermined number being greater than one; ordering the transmission of a return code towards an output of the memory as a function of the content of the counter, and hence of the number of erasure cycles needed for the erasure operation, when the voltage read is the voltage expected after at least two erasure cycles, as well as when the content of the counter has reached the predetermined number.

Claim 2

A method for the erasure of EEPROM memory cells contained in a memory, said method consisting in: opening and initializing a counter in a random-access memory associated with an erasure control processor at the start of an operation for erasing a memory cell of said memory; said operation for erasing comprising erasure cycles, carrying out an erasure cycle on said memory cell, then a reading cycle for reading an actual status voltage of said memory cell and a comparison of the voltage read with an expected voltage corresponding to an erased state of said memory cell; when said read and expected voltages are different, triggering the iteration of the counter and a new erasure and reading cycle, then a comparison, for as long as the content of the counter remains smaller than a predetermined number, said predetermined number being greater than one; ordering the transmission of a return code towards an output of the memory as a function of the content of the counter, and hence of the number of erasure cycles needed for the erasure operation, when the voltage read is the voltage expected after at least two erasure cycles, as well as when the content of the counter has reached the predetermined number.

Claim 4

A device comprising a memory constituted by EEPROM type memory cells associated with a processor, means for opening at the start of each operation of erasure a counter in a random-access memory (RAM) of the processor, and logic means for selectively triggering a return code as a function of the state of the counter at the end of the erasure operation, said selective triggering means including means for counting contents of the counter, and said counter including means for counting a number of erasure cycles in excess of one needed for an erasure operation, as well as when the contents of the counter has reached a predetermined number.

Claim 5

A device comprising a memory constituted by EEPROM type memory cells associated with a processor, means for opening at the start of each operation of erasure a counter in a random-access memory (RAM) of the processor, and logic means for selectively triggering a return code as a function of the state of the counter at the end of the erasure operation, said selective triggering means including means for counting contents of the counter, and said counter including means for counting a number of erasure cycles in excess of one needed for an erasure operation, as well as when the contents of the counter has reached a predetermined number.

Claim 6

A method of erasure according to one of the claims 1 or 2, wherein said EEPROM memory cells are not supplied except during a reading, writing and interrogation of said memory.

Claim 8

A method for erasure of EEPROM memory cells, said method comprising the steps of (a) initializing a counter in a random-access memory associated with an erasure control processor at the start of an operation for erasing a memory cell; (b) carrying out an erasure cycle of said memory cell, (c) then carrying out a reading cycle of said memory cell, and (d) comparing a voltage read with an expected voltage corresponding to an erased state of said memory cell; (e) when said read and said expected voltages are different, triggering an iteration of the counter, and carrying out a new erasure, reading cycle, and comparison and repeating said step (e) for as long as the content of the counter remains smaller than a predetermined whole number which is greater than two, and, (f) generating a return code as a function of the content of the counter, and hence of the number of erasure cycles needed for the erasure operation, when the voltage read is the voltage expected after at least two erasure cycles, as well as when the content of the counter has reached the predetermined number.

Claim 9

A method for erasure of EEPROM memory cells, said method comprising the steps of (a) initializing a counter in a random-access memory associated with an erasure control processor at the start of an operation for erasing a memory cell; (b) carrying out an erasure cycle of said memory cell, (c) then carrying out a reading cycle of said memory cell, and (d) comparing a voltage read with an expected voltage corresponding to an erased state of said memory cell; (e) when said read and said expected voltages are different, triggering an iteration of the counter, and carrying out a new erasure, reading cycle, and comparison and repeating said step (e) for as long as the content of the counter remains smaller than a predetermined whole number which is greater than two, and, (f) generating a return code as a function of the content of the counter, and hence of the number of erasure cycles needed for the erasure operation, when the voltage read is the voltage expected after at least two erasure cycles, as well as when the content of the counter has reached the predetermined number.

Claim 11

A device, comprising a processor having RAM, a memory constituted by EEPROM type memory cells associated with said processor means for opening a counter at the start of each operation of erasure in said of the processor, and logic means for triggering a return code as a function of the state of the counter at the end of the erasure operation, further comprising means for incrementing the contents of said counter in accordance with a number of erasure cycles in excess of two needed for an erasure operation of a memory cell.

Claim 12

A device, comprising a processor having RAM, a memory constituted by EEPROM type memory cells associated with said processor means for opening a counter at the start of each operation of erasure in said of the processor, and logic means for triggering a return code as a function of the state of the counter at the end of the erasure operation, further comprising means for incrementing the contents of said counter in accordance with a number of erasure cycles in excess of two needed for an erasure operation of a memory cell.