Programmable logic with carry-in/carry-out between logic blocks

Claim 2

A programmable logic device comprising: an array of AND gates coupled to logic inputs; an OR gate for producing a logic OR of outputs of selected AND gates; an adder for adding an output of one of said AND gates and an output of said OR gate, a carry input to said adder coupled to a multiplexer output, and multiplexer selecting between at least ground and a carry output from an adjacent adder; a flip-flop for storing an output of said adder; an output selection multiplexer selecting between said output of said adder and an output of said flip-flop; and a carry-out multiplexer selecting between a carry-out output of said adder and said carry output of said adjacent adder for output to a second adjacent adder.

Claim 5

The method as recited in claim 2 wherein said step of generating a sum-of-products term comprises a step of addressing an SRAM bit based on a plurality of inputs.

Claim 6

The method as recited in claim 2 wherein said step of producing a sum also produces a carry-out bit to adjacent member of said logic array.

Claim 7

The method as recited in claim 4 further comprising the step of selecting between said carry-in bit and said carry-out bit for input to said adjacent member of said logic array.

Claim 8

The method as recited in claim 2 further comprising the step of selecting between carry-in bit and ground in a multiplexer for input to said step of producing a sum.

Claim 9

The method as recited in claim 2 further comprising the step of storing said sum in a flip-flop.

Claim 10

A programmable logic device comprising: reprogrammable logic for generating at least one sum-of-products term and a control term; a sum-of-products processing circuit, said sum-of-products processing circuit producing a logical XOR of said control term and said sum-of-products term when a carry-in bit from adjacent reprogrammable logic is disabled, and a sum of said carry-in bit, said sum-of-products term, and said control term when said carry-in bit is enabled; and signal storage means coupled to an output of said sum-of-products processing circuit, wherein said reprogrammable logic comprises a plurality of SRAM bits, said sum-of-products term produced by selection of a value stored in one of said SRAM bits.

Claim 11

A programmable logic device comprising: reprogrammable logic for generating at least one sum-of-products term and a control term; a sum-of-products processing circuit, said sum-of-products processing circuit producing a logical XOR of said control term and said sum-of-products term when a carry-in bit from adjacent reprogrammable logic is disabled, and a sum of said carry-in bit, said sum-of-products term, and said control term when said carry-in bit is enabled; and signal storage means coupled to an output of said sum-of-products processing circuit, wherein said reprogrammable logic comprises a plurality of SRAM bits, said sum-of-products term produced by selection of a value stored in one of said SRAM bits.

Claim 12

A programmable logic device comprising: reprogrammable logic for generating at least one sum-of-products term and a control term; a sum-of-products processing circuit, said sum-of-products processing circuit producing a logical XOR of said control term and said sum-of-products term when a carry-in bit from adjacent reprogrammable logic is disabled, and a sum of said carry-in bit, said sum-of-products term, and said control term when said carry-in bit is enabled, wherein said sum-of-products processing circuit is further adapted to produce a carry-out bit coupled to an adjacent sum-of-products processing circuit; signal storage means coupled to an output of said sum-of-products processing circuit; and a multiplexer coupled to said carry-out bit and said carry-in bit, said multiplexer selecting between output of said carry-out bit and said carry-in bit for input to adjacent sum-of-products processing circuitry.

Claim 13

A programmable logic device comprising: reprogrammable logic for generating at least one sum-of-products term and a control term; a sum-of-products processing circuit, said sum-of-products processing circuit producing a logical XOR of said control term and said sum-of-products term when a carry-in bit from adjacent reprogrammable logic is disabled, and a sum of said carry-in bit, said sum-of-products term, and said control term when said carry-in bit is enabled, wherein said sum-of-products processing circuit is further adapted to produce a carry-out bit coupled to an adjacent sum-of-products processing circuit; signal storage means coupled to an output of said sum-of-products processing circuit; and a multiplexer coupled to said carry-out bit and said carry-in bit, said multiplexer selecting between output of said carry-out bit and said carry-in bit for input to adjacent sum-of-products processing circuitry.

Claim 14

A programmable logic device comprising: reprogrammable logic for generating at least one sum-of-products term and a control term; a sum-of-products processing circuit, said sum-of-products processing circuit producing a logical XOR or said control term and said sum-of-products term when a carry-in bit from adjacent reprogrammable logic is disabled, and a sum of said carry-in bit, said sum-of-products term, and said control term when said carry-in bit is enabled; signal storage means coupled to an output of said sum-of-products processing circuit; an OR gate for ORing outputs of a plurality of switches; an input to said OR gate coupled to an output of an OR gate in first adjacent programmable logic; and an output of said OR gate selectively coupled to an input of an OR gate in second adjacent reprogrammable logic.

Claim 15

A programmable logic device comprising: reprogrammable logic for generating at least one sum-of-products term and a control term; a sum-of-products processing circuit, said sum-of-products processing circuit producing a logical XOR or said control term and said sum-of-products term when a carry-in bit from adjacent reprogrammable logic is disabled, and a sum of said carry-in bit, said sum-of-products term, and said control term when said carry-in bit is enabled; signal storage means coupled to an output of said sum-of-products processing circuit; an OR gate for ORing outputs of a plurality of switches; an input to said OR gate coupled to an output of an OR gate in first adjacent programmable logic; and an output of said OR gate selectively coupled to an input of an OR gate in second adjacent reprogrammable logic.

Claim 16

A programmable logic device comprising: reprogrammable logic for generating at least one sum-of-products term and a control term, said control term a logical AND of selected programmable logic inputs; a sum-of-products processing circuit, said sum-of-products processing circuit producing a logical XOR of said control term and said sum-of-products term when a carry-in bit from adjacent reprogrammable logic is disabled, and a sum of said carry-in bit, said sum-of-products term, and said control term when said carry-in bit is enabled; and signal storage means coupled to an output of said sum-of-products processing circuit.

Claim 17

A programmable logic device comprising: reprogrammable logic for generating at least one sum-of-products term and a control term, said control term a logical AND of selected programmable logic inputs; a sum-of-products processing circuit, said sum-of-products processing circuit producing a logical XOR of said control term and said sum-of-products term when a carry-in bit from adjacent reprogrammable logic is disabled, and a sum of said carry-in bit, said sum-of-products term, and said control term when said carry-in bit is enabled; and signal storage means coupled to an output of said sum-of-products processing circuit.

Claim 18

A programmable logic device as recited in claims 8, 9, 10 or 11 wherein said reprogrammable logic comprises a plurality of AND gates selectively coupled to plural input lines.

Claim 19

A programmable logic device as recited in claims 9, 10 or 11 wherein said reprogrammable logic comprises a plurality of SRAM bits, said sum-of-products term produced by selection of a value stored in one of said SRAM bits.

Claim 20

A programmable logic device as recited in claims 8, 10 or 11 wherein said sum-of-products processing circuit is further adapted to produce a carry-out bit coupled to an adjacent sum-of-products processing circuit.

Claim 21

A programmable logic device as recited in claim 14 further comprising a multiplexer coupled to said carry-out bit and said carry-in bit, said multiplexer selecting between output of said carry-out bit and said carry-in bit for input to adjacent sum-of-products processing circuitry.

Claim 22

A programmable logic device as recited in claims 8, 9, 10 or 11 wherein said carry-in bit is enabled or disabled with a multiplexer that selects among input of said carry-in bit and ground for use in said sum-of-products processing circuit.

Claim 23

A programmable logic device as recited in claims 8, 9, 10 or 11 wherein said signal storage circuit is configurable as a d-type flip-flop.

Claim 24

A programmable logic device as recited in claims 8, 9, 10 or 11 wherein said signal storage circuit is configurable as a d-type flip-flop, a t-type flip-flop, a jk-type flip-flop, or a sr-type flip-flop depending on configuration control information stored in said logic device.

Claim 25

A programmable logic device as recited in claims 8, 9 or 11 wherein said reprogrammable logic further comprises: an OR gate for ORing outputs of a plurality of switches; an input to said OR gate coupled to an output of an OR gate in first adjacent programmable logic; and an output of said OR gate selectively coupled to an input of an OR gate in second adjacent reprogrammable logic.

Claim 26

A programmable logic device as recited in claim 16 wherein said multiplexer selects among input of said carry-in bit, ground, and a logic level 1, whereby said programmable logic device may implement a subtract function.

Claim 27

A programmable logic device as recited in claims 8, 9 or 10 wherein said control term is a logical AND of selected programmable logic inputs.