US5358906A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making integrated circuit package containing inner leads with knurled surfaces
Assignee: SK Hynix Inc
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Filing: 1993-10-22
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Granted: 1994-10-25
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Expires: 2013-10-22
Abstract
Abstract A lead on chip package comprising a semiconductor chip having a plurality of bonding pads and a plurality of minute protrusions formed at both side portions of the upper surface thereof, an insulating film made of a fluoroethylene film having knurled surfaces, and a plurality of inner leads each directly connected to each corresponding bonding pad of the semiconductor chip and provided with knurled surfaces. The formation of minute protrusions is accomplished by using a radio frequency (RF)-sputtering process at a low temperature. The formation of the knurled surfaces at the inner leads can be accomplished by passing the inner leads between rollers each having a knurled outer surface or by coating a nodule or dendrite layer over the surfaces of inner leads by an electro-plating using a high current density. Using the fluoroethylene film, the insulating film can reduce in thickness. By virtue of the knurled surfaces formed at the inner leads and the insulating film, the adhesion can be improved. It is also possible to prevent an occurrence of parasitic capacitance. As a result, there is provided an effect of assisting packages to be laminate.
Inventors
- 👤 Hee G. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:52
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W70/421; H10W70/424; H10W70/464; H10W70/466; H10W72/00; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/851; H10W72/853; H10W72/865; H10W72/90; H10W72/931; H10W72/932; H10W74/00; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
217 words
A method of making a lead on chip package comprising the steps of: preparing a lead frame including a paddle, a plurality of inner leads and a plurality of outer leads each extending from each corresponding inner lead; die bonding a semiconductor chip to the paddle of the lead frame, the semiconductor chip having a plurality of bonding pads arranged in a line at the center portion of the upper surface of the semiconductor chip; forming a plurality of minute protrusions at both side portions of the upper surface of the semiconductor chip except for its portions corresponding to the bonding pads; forming an insulating film over the protrusion-carrying upper surface of the semiconductor chip, the insulating film having knurled surfaces at its upper and lower surfaces; forming knurled surfaces at each of the inner leads, one of the knurled surfaces of each inner lead being in contact with one of the knurled surfaces of the insulating film; forming a solder over each pad of the semiconductor chip; soldering each inner lead to each corresponding solder so as to connect electrically the inner leads to the semiconductor chip; molding a predetermined part including the semiconductor chip, the insulating film and the inner leads so as to form a package body; and trimming and shaping the package body.
Claim 2
Independent Claim
217 words
A method of making a lead on chip package comprising the steps of: preparing a lead frame including a paddle, a plurality of inner leads and a plurality of outer leads each extending from each corresponding inner lead; die bonding a semiconductor chip to the paddle of the lead frame, the semiconductor chip having a plurality of bonding pads arranged in a line at the center portion of the upper surface of the semiconductor chip; forming a plurality of minute protrusions at both side portions of the upper surface of the semiconductor chip except for its portions corresponding to the bonding pads; forming an insulating film over the protrusion-carrying upper surface of the semiconductor chip, the insulating film having knurled surfaces at its upper and lower surfaces; forming knurled surfaces at each of the inner leads, one of the knurled surfaces of each inner lead being in contact with one of the knurled surfaces of the insulating film; forming a solder over each pad of the semiconductor chip; soldering each inner lead to each corresponding solder so as to connect electrically the inner leads to the semiconductor chip; molding a predetermined part including the semiconductor chip, the insulating film and the inner leads so as to form a package body; and trimming and shaping the package body.
Claim 3
Dependent Claim
37 words
A method of making a lead on chip package in accordance with claim 1, wherein the step of forming a plurality of minute protrusions is carried out by using a radio frequency-sputtering method at a low temperature.
Claim 4
Dependent Claim
29 words
A method of making a lead on chip package in accordance with claim 2, wherein the minute protrusions are made of Si 3 N 4 or SiO 2 .
Claim 5
Dependent Claim
27 words
A method of making a lead on chip package in accordance with claim 3, wherein the minute protrusions have a thickness of 400 Å to 500 Å.
Claim 6
Dependent Claim
69 words
A method of making a lead on chip package in accordance with claim 3, wherein the inner leads have a construction that a portion of each inner lead connected to each corresponding bonding pad of the semiconductor chip has a width smaller than a portion of each inner lead connected to each corresponding outer lead, so that they are connected to the corresponding bonding pads in an alternate manner.
Claim 7
Dependent Claim
38 words
A method of making a lead on chip package in accordance with claim 3, wherein the step of forming the knurled surfaces at each inner lead is carried out by using rollers each having a knurled outer surface.
Claim 8
Dependent Claim
52 words
A method of making a lead on chip package in accordance with claim 3, wherein the step of forming the knurled surfaces at each inner lead is carried out by using electro-plating using a high current density or by coating a nodule or dendrite layer over the surfaces of each inner lead.
Claim 9
Independent Claim
244 words
A method of making a lead on chip package comprising the steps of: preparing a lead frame including a paddle, a plurality of inner leads and a plurality of outer leads each formed separately from each corresponding inner lead; die bonding a semiconductor chip to the paddle of the lead frame, the semiconductor chip having a plurality of bonding pads arranged in a line at the center portion of the upper surface of the semiconductor chip; forming a plurality of minute protrusions at both side portions of the upper surface of the semiconductor chip except for its portions corresponding to the bonding pads; forming an insulating film over the protrusion-carrying upper surface of the semiconductor chip, the insulating film having knurled surfaces at its upper and lower surfaces; forming knurled surfaces at each of the inner leads, one of the knurled surfaces of each inner lead being in contact with one of the knurled surfaces of the insulating film; forming a solder over each pad of the semiconductor chip; soldering one end of each inner lead to each corresponding solder so as to connect electrically the inner leads to the semiconductor chip; soldering the other end of each inner lead to one end of each outer lead so as to connect them to each other; molding a predetermined part including the semiconductor chip, the insulating film and the inner leads so as to form a package body; and trimming and shaping the package body.
Claim 10
Independent Claim
244 words
A method of making a lead on chip package comprising the steps of: preparing a lead frame including a paddle, a plurality of inner leads and a plurality of outer leads each formed separately from each corresponding inner lead; die bonding a semiconductor chip to the paddle of the lead frame, the semiconductor chip having a plurality of bonding pads arranged in a line at the center portion of the upper surface of the semiconductor chip; forming a plurality of minute protrusions at both side portions of the upper surface of the semiconductor chip except for its portions corresponding to the bonding pads; forming an insulating film over the protrusion-carrying upper surface of the semiconductor chip, the insulating film having knurled surfaces at its upper and lower surfaces; forming knurled surfaces at each of the inner leads, one of the knurled surfaces of each inner lead being in contact with one of the knurled surfaces of the insulating film; forming a solder over each pad of the semiconductor chip; soldering one end of each inner lead to each corresponding solder so as to connect electrically the inner leads to the semiconductor chip; soldering the other end of each inner lead to one end of each outer lead so as to connect them to each other; molding a predetermined part including the semiconductor chip, the insulating film and the inner leads so as to form a package body; and trimming and shaping the package body.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-10-24 | 1998-04-25 | 1998-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-24 | 2002-04-25 | 2002-10-25 | $3760.00 | Window Closed / Lapsed |
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