Time-domain boundary buffer method and apparatus

Claim 2

A time domain boundary buffer circuit for coupling a first time domain bus to a second time domain, comprising: a plurality of data inputs coupled to said first time domain bus; a strobe input coupled to a strobe signal of said first time domain bus; a clock input coupled to a clock signal of said first time domain bus; a data ready circuit coupled to said strobe input and to said clock input, for capturing transitions at said strobe input responsive to said clock input; a data buffer circuit coupled to said data inputs, and said strobe input for synchronizing data from said first time domain bus into said second time domain; and said data buffer circuit receiving said data at said data inputs in response to a transition at said strobe input, and subsequently synchronizing said data into said second time domain.

Claim 3

The time domain boundary buffer circuit of claim 1, wherein said data ready circuit comprises: a first clocked memory coupled to said strobe signal and to said clock signal from said bus, and having an output; a second clocked memory coupled to said first clocked memory and further coupled to a second clock signal related to said second time domain, said second clocked memory capturing the output of said first clocked memory responsive to said second clock signal, and having an output; a third clocked memory coupled to said second clocked memory and to said second clock signal, said third clocked memory capturing the output of said second clocked memory responsive to a transition in said second clock signal; self clearing logic coupled to the output of said third clocked memory and of a clear input to said first clocked memory, said self clearing logic clearing said first clocked memory on the transition of the output of said third clocked memory; and said data ready circuit capturing a transition at said strobe input in said first clocked memory responsive to the clock signal from said bus, and subsequently synchronizing said captured transition to said second clock signal.

Claim 4

The data ready circuit of claim 2, wherein said self clearing logic comprises a logic NOR gate.

Claim 5

The data ready circuit of claim 2, wherein said self clearing logic comprises a logic NAND gate.

Claim 6

The data ready circuit of claim 2, wherein each of said clocked memories comprises an edge triggered flip flop circuit.

Claim 7

The data ready circuit of claim 2, wherein each of said clocked memories comprises a master slave dual phase flip flop.

Claim 8

The time domain boundary buffer circuit of claim 1, wherein said data buffer circuit comprises: a first clocked memory coupled to said data inputs from said first time domain bus and being clocked by said clock from said first time domain bus, and having a hold function; a second clocked memory coupled to said first clocked memory and having a hold function, said second clocked memory being clocked by a clock signal related to said second time domain; and the first clocked memory selectively capturing said data signals from said first time domain bus responsive to said strobe signal from said first time domain bus and said second clocked memory selectively receiving said captured data from said first clocked memory responsive to said clock signal from said second time domain.

Claim 9

The data buffer circuit of claim 7, wherein said first and second clocked memories each comprise edge triggered flip-flop circuits.

Claim 12

The method of claim 9, wherein said step of providing a data ready circuit further comprises the steps of: providing a first clocked memory coupled to said enable input and to said clock input from said bus, and having an output; providing a second clocked memory coupled to said output of said first clocked memory and further coupled to a second clock signal related to said second time domain, said second clocked memory capturing the output of said first clocked memory responsive to said second clock signal, said second clocked memory having an output; providing a third clocked memory coupled to said output of said second clocked memory and to said second clock signal, said third clocked memory capturing the output of said second clocked memory responsive to a transition in said second clock signal, said third clocked memory having an output; providing self clearing logic coupled to the output of said third clocked memory and of a clear input to said first clocked memory, said self clearing logic clearing said first clocked memory on the transition of the output of said third clocked memory; and capturing a transition at said enable input in said first clocked memory responsive to said first clock signal from said bus, and subsequently synchronizing said captured transition to said second clock signal.

Claim 13

The method of claim 10, wherein the step of providing self clearing logic comprises the step of providing a logic NOR gate coupled between the output of said third clocked memory and said clear input of said first clocked memory, and further coupled to a reset input terminal from said bus, said NOR gate selectively clearing the first clocked memory responsive to a transition in the output of said third clocked memory, and alternatively responsive to a transition at said reset input terminal.

Claim 14

The method of claim 11, wherein said steps of providing first, second and third clocked memories each comprise the step of providing an edge triggered flip flop circuit.

Claim 15

The method of claim 11, wherein said steps of providing first, second and third clocked memories each comprise the step of providing a master slave dual phase clock flip flop circuit.

Claim 16

The method of claim 9, wherein said stop of providing said data buffer circuit comprises the steps of: providing a first clocked memory coupled to said data inputs from said bus and being clocked by said clock input from said bus, said first clocked memory having a hold function and an output; providing a second clocked memory coupled to said output of said first clocked memory and having a hold function, said second clocked memory being clocked by a clock signal related to said second time domain, said second clocked memory having an output; and selectively capturing one or more data from said bus in said first clocked memory responsive to said strobe signal from said bus, and subsequently capturing said data from said first clocked memory into said second clocked memory responsive to a second clock signal from said second time domain.

Claim 17

The method of claim 14 and further comprising the step of providing said second clocked memory to receive data from said first clocked memory.

Claim 18

The method of claim 15 wherein said steps of providing first and second clocked memories each comprise the step of providing a master slave dual phase clocked flip-flop circuit.

Claim 19

The method of claim 14 wherein said steps of providing first and second clocked memories each comprise the step of providing an edge triggered flip-flop circuit.

Claim 20

An integrated circuit having an interface for receiving data from an asynchronous bus, comprising: a time boundary buffer circuit coupled to said asynchronous bus, for synchronizing data received from said asynchronous bus; a strobe input coupled to a strobe signal from said asynchronous bus; user application circuitry coupled to said time boundary buffer circuit and to outputs of said integrated circuit; a clock input coupled to said time boundary buffer circuit and to said user application circuitry, to provide a clock signal related to a synchronous time domain within said integrated circuit; and said user application circuitry selectively receiving and operating on data transmitted on said asynchronous bus by using said time boundary buffer circuit for synchronizing said data into said synchronous time domain responsive to said strobe signal.

Claim 21

An integrated circuit having an interface for receiving data from an asynchronous bus, comprising: a time boundary buffer circuit coupled to said asynchronous bus, for synchronizing data received from said asynchronous bus; a strobe input coupled to a strobe signal from said asynchronous bus; user application circuitry coupled to said time boundary buffer circuit and to outputs of said integrated circuit; a clock input coupled to said time boundary buffer circuit and to said user application circuitry, to provide a clock signal related to a synchronous time domain within said integrated circuit; and said user application circuitry selectively receiving and operating on data transmitted on said asynchronous bus by using said time boundary buffer circuit for synchronizing said data into said synchronous time domain responsive to said strobe signal.

Claim 22

The integrated circuit of claim 18, wherein said user application circuitry comprises a memory.

Claim 23

The integrated circuit of claim 18, wherein said user application circuitry comprises an arithmetic logic function.

Claim 24

The integrated circuit of claim 18, wherein said user application circuitry comprises a user programmable logic array.

Claim 25

The integrated circuit of claim 18, wherein said user application circuitry comprises a processor.

Claim 26

The integrated circuit of claim 18, wherein said time boundary buffer circuit comprises: data inputs coupled to said asynchronous bus; a strobe input coupled to said strobe signal of said asynchronous bus; a data ready circuit coupled to said strobe input to capture transitions of said strobe signal; a data buffer circuit coupled to said data inputs, said data buffer circuit synchronizing data from said bus into said synchronous time domain; and said time boundary buffer circuit receiving said data at said data inputs into said data buffer circuit in response to a transition at said strobe input, and further synchronizing said data into said synchronous time domain.

Claim 27

The time domain boundary buffer circuit of claim 23 wherein said data ready circuit comprises: a first memory coupled to said strobe input for capturing said strobe signal, and having an output; a second memory coupled to said first memory and further coupled to said clock signal, to capture the output of said first clocked memory responsive to said clock signal, and having an output; a third memory coupled to said second memory and to said clock signal, said third memory capturing the output of said second memory responsive to a transition in said clock signal; and said data ready circuit capturing a transition at said strobe input and subsequently synchronizing said captured transition to said clock signal.

Claim 28

The time domain boundary buffer circuit of claim 23, wherein said data buffer circuit comprises: a first clocked memory coupled to said data inputs from said asynchronous bus and being clocked by a second clock input from said asynchronous bus, and having a hold function; a second clocked memory coupled to said first clocked memory and having a hold function, said second clocked memory being clocked by said clock signal related to said synchronous time domain; and the first clocked memory selectively capturing data from said asynchronous bus responsive to said strobe signal from said asynchronous bus and said second clocked memory selectively receiving said data from said first clocked memory responsive to said clock signal from said synchronous time domain.