Method and apparatus for volume switched gain control

Claim 3

A method as, claimed in claim 1, wherein: said first providing step includes a step of filtering the first input signal; and said second providing step includes a step of filtering the second input signal.

Claim 4

A method as claimed in claim 1, wherein said determining, processing and adjusting steps are performed by a processor.

Claim 5

A method as claimed in claim 2, wherein said first and second filtering steps each comprise a step of blocking direct current signals to allow only signals having a frequency of greater than approximately one hundred Hertz to pass.

Claim 6

A method as claimed in claim 1, wherein said determining steps comprise steps of: measuring a first peak signal level of the first input signal over a first time interval; measuring a first minimum signal level of the first input signal over a second time interval; measuring a first peak signal level of the second input signal over the first time interval; and measuring a first minimum signal level of the second input signal over the second time interval.

Claim 7

A method as claimed in claim 5, wherein said second time interval comprises a series of intervals in a range of approximately ten to 50 milliseconds, concatenated to comprise an interval of less than five seconds in duration.

Claim 10

An apparatus as claimed in claim 7, wherein said processor further is for determining a lower level of said first audio input signals over a short time interval and comparing lower levels of said first audio input signals from a series of short time intervals for determining said minimum level occurring within said series of short time intervals.

Claim 11

An apparatus as claimed in claim 8, wherein said short time interval comprises a time interval in a range of from 20 to 40 milliseconds.

Claim 12

An apparatus as claimed in claim 8, wherein said series of short time intervals comprise an interval in a range of from one-half to 3 seconds.

Claim 13

An apparatus as claimed in claim 7, wherein said processor comprises a digital signal processor.

Claim 14

An apparatus as claimed in claim 7, wherein said processor comprises an analog signal processor.

Claim 15

An apparatus as claimed in claim 7, wherein said first audio input further includes: a first filter coupled to said first audio input, said first filter for conditioning first audio input signals from said first audio input; and a first analog to digital conversion circuit coupled to said first filter and to said processor, said first analog to digital conversion circuit for converting said first audio input signals from analog signals to digital signals.

Claim 16

An apparatus as claimed in claim 7 wherein said second audio input further includes: a second filter coupled to said second audio input, said second filter for conditioning second audio input signals from said second audio input; and a second analog to digital conversion circuit coupled to said second filter and to said processor, said second analog to digital conversion circuit for converting said first audio input signals from analog signals to digital signals.

Claim 17

An apparatus as claimed in claim 8, wherein said short time interval comprises a time interval of approximately 30 milliseconds.

Claim 18

A full duplex signal communications channel including signal processing apparatus, said signal processing apparatus comprising: a first input for providing a first signal; a second input for providing a second signal; a processor coupled to said first and second inputs, said processor for estimating an peak level and a minimum level of each of said first and second input signals during discrete time intervals; a first signal level regulator coupled to said first input and to a first output, said first signal level regulator for delivering a first output signal having a first gain G T from said first input signal; a second signal level regulator coupled to said second input and to a second output, said second signal level regulator for delivering a second output signal having a second gain G R from said second input signals; and a gain adjuster coupled to said processor and to said first and second signal level regulators, said gain adjuster for providing control signals to said first and second signal level regulators to adjust first and second output signal levels of said first and second output signals in response to said minimum and peak levels of said first and second input signals, wherein said first and second output signal levels are continuously variable over a range, wherein said first and second signal regulators provide said second gain G R according to: ##EQU3##

Claim 19

A full duplex signal communications channel including signal processing apparatus, said signal processing apparatus comprising: a first input for providing a first signal; a second input for providing a second signal; a processor coupled to said first and second inputs, said processor for estimating an peak level and a minimum level of each of said first and second input signals during discrete time intervals; a first signal level regulator coupled to said first input and to a first output, said first signal level regulator for delivering a first output signal having a first gain G T from said first input signal; a second signal level regulator coupled to said second input and to a second output, said second signal level regulator for delivering a second output signal having a second gain G R from said second input signals; and a gain adjuster coupled to said processor and to said first and second signal level regulators, said gain adjuster for providing control signals to said first and second signal level regulators to adjust first and second output signal levels of said first and second output signals in response to said minimum and peak levels of said first and second input signals, wherein said first and second output signal levels are continuously variable over a range, wherein said first and second signal regulators provide said second gain G R according to: ##EQU3##

Claim 20

A signal processing apparatus as claimed in claim 16, wherein said first and second signal regulators provide said first gain G T according to: G.sub.T.sbsb.n =G.sub.T.sbsb.n-1 +S{G.sub.T.sbsb.n-1 (E.sub.T -2N.sub.T)-(G.sub.L /G.sub.T.sbsb.n-1)(E.sub.R -2N.sub.R)}, wherein subscripts n and n-1 refer to present and previous discrete time intervals, respectively, subscripts T and R refer to said first and second signal regulators, respectively, G L refers to a product of said first gain of said first signal regulator and said second gain of said second signal regulator during previous discrete time interval n-1, S represents a dimensionless scale factor, E represents peak speech amplitudes, N represents minimum speech amplitudes.

Claim 21

A signal processing apparatus as claimed in claim 16, comprising: a first digital to analog converter circuit coupled to said first signal level regulator, said first digital to analog converter circuit for providing said first output signal; and a second digital to analog converter circuit coupled to said second signal level regulator, said second digital to analog converter circuit for providing said second output signal.

Claim 22

A signal processing apparatus as claimed in claim 18, wherein said processor, said first and second signal level regulators and said gain adjustment device comprise digital circuitry.

Claim 23

A signal processing apparatus as claimed in claim 16, wherein: said first signal input includes a first analog to digital converter, said first analog to digital converter for converting said first input signal from analog to digital; and said second signal input includes a second analog to digital converter, said second analog to digital converter for converting said second input signal from analog to digital.