Nonvolatile capacitor random access memory

Claim 2

A memory cell having: (a) one or two transistors; and (b) a capacitor programmable into a high or a low capacitance, said capacitor comprising; (i) a nonvolatile gate, (ii) a nonvolatile stack thereunder for storing charge, (iii) a heavily doped n+ type region adjacent on at least one side to said nonvolatile gate wherein said n+ region extends beneath said stack, (iv) an n-type tank disposed beneath said nonvolatile stack to a depth and electrically connected to said n+ type region, and (v) a p-type substrate underlying the n+ region and the n-type tank.

Claim 3

A memory array comprising cells, each memory cell comprising: (a) one or two transistors; and (b) a programmable capacitor, said capacitor comprising; (i) a nonvolatile gate, (ii) a nonvolatile stack thereunder for storing charge, (iii) a heavily doped n+ type region adjacent on at least one side to said nonvolatile gate wherein said n+ region extends beneath said stack, (iv) an n-type tank disposed beneath said nonvolatile stack to a depth and electrically connected to said n+ type region, and (v) a p-type substrate underlying the n+ region and the n-type tank.

Claim 4

A memory array comprising cells, each memory cell comprising: (a) one or two transistors; and (b) a programmable capacitor, said capacitor comprising; (i) a nonvolatile gate, (ii) a nonvolatile stack thereunder for storing charge, (iii) a heavily doped n+ type region adjacent on at least one side to said nonvolatile gate wherein said n+ region extends beneath said stack, (iv) an n-type tank disposed beneath said nonvolatile stack to a depth and electrically connected to said n+ type region, and (v) a p-type substrate underlying the n+ region and the n-type tank.

Claim 5

The memory array according to claim 2 in which at least one memory cell is electrically programmed into a state of high capacitance and operated as volatile storage dynamic RAM cells and in which at least one memory cell is programmed either into a state of high capacitance or low capacitance and read as nonvolatile data depending on the capacitance state.

Claim 6

The memory array according to claim 3 in which volatile data is written into the memory cells in the high capacitance state and is transferred to nonvolatile by first using the volatile data from one row of memory cells activated by one word line to set sense amplifiers to a high or low voltage state depending on the volatile data and is then converted to nonvolatile by means of a large positive voltage pulse on the storage gate line parallel to the activated word line with the conversion of the cell to the nonvolatile low capacitance state depending on the difference in the voltage stored on the sense amplifier connected to the n-tank of the cell through the transfer gate and the voltage on the storage gate line.

Claim 7

A memory array according to claim 3 in which the nonvolatile data can be converted to volatile data by means of the read operations which set the sense amplifier to a high or low voltage depending on the nonvolatile state of the cells in one row of cells followed by an isolation of these sense amplifiers from the bit lines followed by the application of a large positive voltage to all bit lines with consequent programming of all memory cells on the row addressed followed by writing the volatile data back onto the cells using the voltages previously stored on the sense amplifiers.

Claim 8

The memory cell of claim 1 wherein a depletion region formed in the n-type tank at a boundary between the n-type tank and the p-type substrate by a positive programming voltage applied to the n+ region is smaller than the depth of the n-type tank.

Claim 9

The memory cell of claim 1 wherein a breakdown voltage of a junction formed by the n+ region and the n-tank is significantly larger than the voltage required for reading the cell.