US5357458A
Expired / Lapsed
US
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System for allowing a content addressable memory to operate with multiple power voltage levels
Assignee: Cypress Semiconductor Corp
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Filing: 1993-06-25
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Granted: 1994-10-18
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Expires: 2013-06-25
Abstract
Abstract A system for allowing a content addressable memory (CAM) to operate with first and second power voltage levels including: a first input voltage for providing a first bias to the content addressable memory; a second input voltage for providing a second bias to the content addressable memory; and a selection device coupled to the first input voltage and the second input voltage for decoupling the first input voltage from the content addressable memory and coupling the second input voltage to the content addressable memory in response to coupling the second power voltage level to the content addressable memory. In a specific embodiment the system includes: a first power on reset coupled to the content addressable memory for initializing the content addressable memory when the first power voltage level is initially coupled to the content addressable memory; and a second power on reset coupled to the content addressable memory for initializing the content addressable memory when the second power voltage level is initially coupled to the content addressable memory. The system allows a CAM to operate at a power voltage level of 2.6 to 3.6 volts to reduce power dissipation and at a higher voltage during programming of an electrically programmable memory. The system provides multiple resets to a CAM for proper operation with multiple power supply levels. The system also provides a CAM that allows access to redundant addresses of an electrically programmable read only memory (EPROM) and that allows programming of the EPROM with traditional programming equipment.
Inventors
- 👤 James Yu
- 👤 Tiao-Hua Kuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:04
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C15/00; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/30; G11C29/78; G11C29/785; G11C29/789; G11C5/00; G11C5/14; G11C5/143
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
98 words
A system for allowing a content addressable memory to operate with first and second power voltage levels comprising: means for providing a first bias voltage to the content addressable memory; means for providing a second bias voltage to the content addressable memory; and selection means coupled to the first bias voltage means and the second bias voltage means for decoupling the first bias voltage providing means from the content addressable memory and coupling the second bias voltage providing means to the content addressable memory in response to coupling the second power voltage level to the content addressable memory.
Claim 2
Independent Claim
98 words
A system for allowing a content addressable memory to operate with first and second power voltage levels comprising: means for providing a first bias voltage to the content addressable memory; means for providing a second bias voltage to the content addressable memory; and selection means coupled to the first bias voltage means and the second bias voltage means for decoupling the first bias voltage providing means from the content addressable memory and coupling the second bias voltage providing means to the content addressable memory in response to coupling the second power voltage level to the content addressable memory.
Claim 3
Dependent Claim
70 words
The system of claim 1 further comprising: first power on reset means coupled to the content addressable memory for initializing the content addressable memory when the first power voltage level is initially coupled to the content addressable memory; and second power on reset means coupled to the content addressable memory for initializing the content addressable memory when the second power voltage level is initially coupled to the content addressable memory.
Claim 4
Dependent Claim
35 words
The system of claim 2 wherein the selection means further comprises a first sensing means coupled to the selection means for detecting when the second power voltage level is coupled to the content addressable memory.
Claim 5
Dependent Claim
39 words
The system of claim 3 wherein the first power on reset means further comprises a second sensing means coupled to the content addressable memory for detecting when the first power voltage level is coupled to the content addressable memory.
Claim 6
Dependent Claim
43 words
The system of claim 4 wherein the second power on reset means further comprises a third sensing means coupled to the first sensing means for detecting when the first sensing means detects the second power voltage level coupled to the content addressable memory.
Claim 7
Dependent Claim
39 words
The system of claim 5 wherein the content addressable memory further comprises: a programmable memory having an input bias voltage coupled to the selection means and an output; and a latch coupled to the output of the programmable memory.
Claim 8
Dependent Claim
24 words
The system of claim 6 wherein the first power on reset means and the second power on reset means are coupled to the latch.
Claim 9
Dependent Claim
30 words
The system of claim 7 wherein the selection means couples either the first input voltage means or the second input voltage means to the input bias of the programmable memory.
Claim 10
Dependent Claim
30 words
The system of claim 7 wherein the second power voltage level is greater than 11 volts and wherein the first power voltage level is between 2.6 volts and 3.6 volts.
Claim 11
Dependent Claim
30 words
The system of claim 7 wherein the second power voltage level is greater than 6 volts and wherein the first power voltage level is between 2.6 volts and 3.6 volts.
Claim 12
Dependent Claim
192 words
An improved programmable read only memory having redundant addresses and operable with first and second power voltage levels comprising: content addressable memory means for controlling access to the redundant addresses of the programmable read only memory and for storing addresses of the programmable read only memory; first input voltage means for providing a first bias to the content addressable memory; second input voltage means for providing a second bias to the content addressable memory; selection means coupled to the first input voltage means and the second input voltage means for decoupling the first input voltage means from the content addressable memory and coupling the second input voltage means to the content addressable memory in response to coupling the second power voltage level to the programmable read only memory; first power on reset means coupled to the content addressable memory for initializing the content addressable memory when the first power voltage level is initially coupled to the content addressable memory; and second power on reset means coupled to the content addressable memory for initializing the content addressable memory when the second power voltage level is initially coupled to the programmable read only memory.
Claim 13
Dependent Claim
192 words
An improved programmable read only memory having redundant addresses and operable with first and second power voltage levels comprising: content addressable memory means for controlling access to the redundant addresses of the programmable read only memory and for storing addresses of the programmable read only memory; first input voltage means for providing a first bias to the content addressable memory; second input voltage means for providing a second bias to the content addressable memory; selection means coupled to the first input voltage means and the second input voltage means for decoupling the first input voltage means from the content addressable memory and coupling the second input voltage means to the content addressable memory in response to coupling the second power voltage level to the programmable read only memory; first power on reset means coupled to the content addressable memory for initializing the content addressable memory when the first power voltage level is initially coupled to the content addressable memory; and second power on reset means coupled to the content addressable memory for initializing the content addressable memory when the second power voltage level is initially coupled to the programmable read only memory.
Claim 14
Dependent Claim
69 words
The improved programmable read only memory of claim 11 further comprising: comparator means coupled to the content addressable memory for matching an address for accessing the programmable read only memory to the addresses stored in the content addressable memory; and conversion means coupled to the comparator means for mapping the address for accessing the programmable read only memory to a respective redundant address of the programmable read only memory.
Claim 15
Dependent Claim
48 words
The improved programmable read only memory of claim 12 wherein the content addressable memory further comprises: a programmable memory having an input bias coupled to the selection means and an output; and a latch coupled to the output of the programmable memory and coupled to the comparator means.
Claim 16
Dependent Claim
24 words
The system of claim 13 wherein the first power on reset means and the second power on reset means are coupled to the latch.
Claim 17
Dependent Claim
30 words
The system of claim 14 wherein the selection means couples either the first input voltage means or the second input voltage means to the input bias of the programmable memory.
Claim 18
Independent Claim
81 words
A system for allowing a content addressable memory to operate with first and second power voltage levels comprising: first power on reset means coupled to the content addressable memory for initializing the content addressable memory when the first power voltage level is initially coupled to the content addressable memory; and second power on reset means coupled to the content addressable memory for initializing the content addressable memory when the second power voltage level is initially coupled to the content addressable memory.
Claim 19
Independent Claim
81 words
A system for allowing a content addressable memory to operate with first and second power voltage levels comprising: first power on reset means coupled to the content addressable memory for initializing the content addressable memory when the first power voltage level is initially coupled to the content addressable memory; and second power on reset means coupled to the content addressable memory for initializing the content addressable memory when the second power voltage level is initially coupled to the content addressable memory.
Claim 20
Dependent Claim
39 words
The system of claim 16 wherein the first power on reset means further comprises a first sensing means coupled to the content addressable memory for detecting when the first power voltage level is coupled to the content addressable memory.
Claim 21
Dependent Claim
39 words
The system of claim 17 wherein the second power on reset means further comprises a second sensing means coupled to the content addressable memory for detecting when the second power voltage level is coupled to the content addressable memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-17 | 1998-04-18 | 1998-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-17 | 2002-04-18 | 2002-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-17 | 2006-04-18 | 2006-10-18 | $7700.00 | Window Closed / Lapsed |