Video decoder with parallel implementation

Claim 2

An image decoder comprising: a demultiplexer for dividing a video signal for a frame into four phases respectively comprising an 8×8 block; a plurality of inverse quantization and inverse discrete cosine transform means for respectively inverse quantizing and inverse discrete cosine transforming said divided video signals of the 8×8 block; phase compensating means for matching each of the phases of respective motion compensation video signals; scanning conversion means for matching respective scanning orders of said inverse quantized and inverse discrete cosine transformed video signals with the motion compensated video signal for each frame to generate a scanning converted video signal for each frame.; an adder for adding said scanning converted video signal for each frame to said motion compensated video signal of the corresponding frame; phase dividing means for dividing the video signal for a frame from said adder into four phases on the X axis; data switching means for controlling order of reading and writing timings of the video signals to be provided to said phase compensating means and the video signals output by said phase dividing means; a plurality of pairs of frame memories for alternately reading and writing the respective phases of the video signals from said data switching means in each of the four phases; address switching means for controlling order of read and write addresses of said plurality of pairs of frame memories so as to alternate between the pairs of frame memories; and address generating means for generating said read and write addresses of said plurality of pairs of frame memories through said address switching means.

Claim 3

An image decoder as claimed in claim 1, wherein said scanning conversion means comprises: a plurality of pairs of tri-state latches for controlling the order of reading and writing timings of the video signals from said plurality of inverse quantization and inverse discrete cosine transform means divided into four phases of 8×8 block in the unit of block; a plurality of pairs of memories for alternately reading and writing the video signals under the control of respective tri-state latch among said plurality of pairs of tri-state latches; a first pair of multiplexers for alternately providing the read and write addresses to said respective pairs of memories; a first plurality of counters for providing the read and write addresses of said respective pairs of memories through said first pair of multiplexers; a second plurality of multiplexers for respectively switching the video signals output from said plurality of pairs of memories in order to alternately provide the switched signals; a third multiplexer for multiplexing the outputs of said second plurality of multiplexers according to the order of the phase compensated video signal; and a second counter for providing selection control signals of said third multiplexer.

Claim 4

An image decoder as claimed in claim 1, wherein said phase compensating means comprises a multiplexer for providing the video signal phase compensated by regarding two lower bits of a motion vector corresponding the X axis as control inputs so as to be matched for the scanning order.

Claim 5

An image decoder as claimed in claim 1, wherein said phase dividing means comprises a demultiplexer for dividing the output signal of said adder into four phases so as to be respectively matched for each of said plurality of pairs of frame memories.

Claim 6

An image decoder as claimed in claim 1, wherein said data switching means comprises: a multiplexer for selecting the respective outputs of frame memories to be read among said respective pairs of frame memories for each phase; a pair of tri-state latches for selecting the respective input lines of frame memories to be written among said respective pairs of frame memories for each phase; and an inverter for inverting the operations of said pair of tri-state latches.

Claim 7

An image decoder comprising: a demultiplexer for dividing a video signal for a frame into four phases respectively comprising an 8×8 block; a plurality of inverse quantization and inverse discrete cosine transform means for respectively inverse quantizing and inverse discrete cosine transforming said divided video signals of the 8×8 block; phase compensating means for matching each of the phases of respective motion compensation video signals; scanning conversion means for matching respective scanning orders of said inverse quantized and inverse discrete cosine transformed video signals with said motion compensated video signal for each frame to generate a scanning converted video signal for each frame; a plurality of adders for respectively adding said scanning converted video signals to said motion compensated video signals for each phase; a multiplexer for multiplexing the video signals output from said plurality of adders in the unit of frame; data switching means for controlling the order of reading and writing timings of the video signals to be provided to said phase compensating means and the video signals output said plurality of adders to be provided to said multiplexer; a plurality of pairs of frame memories for alternately reading and writing the video signals from said data switching means in each of the four phases; address switching means for controlling the order of the read and write addresses of said plurality of pairs of frame memories so as to alternate between the pairs of frame memories; and address generating means for generating said read and write addresses of said plurality of pairs of frame memories through said address switching means.

Claim 8

An image decoder comprising: a demultiplexer for dividing a video signal for a frame into four phases respectively comprising an 8×8 block; a plurality of inverse quantization and inverse discrete cosine transform means for respectively inverse quantizing and inverse discrete cosine transforming said divided video signals of the 8×8 block; phase compensating means for matching each of the phases of respective motion compensation video signals; scanning conversion means for matching respective scanning orders of said inverse quantized and inverse discrete cosine transformed video signals with said motion compensated video signal for each frame to generate a scanning converted video signal for each frame; a plurality of adders for respectively adding said scanning converted video signals to said motion compensated video signals for each phase; a multiplexer for multiplexing the video signals output from said plurality of adders in the unit of frame; data switching means for controlling the order of reading and writing timings of the video signals to be provided to said phase compensating means and the video signals output said plurality of adders to be provided to said multiplexer; a plurality of pairs of frame memories for alternately reading and writing the video signals from said data switching means in each of the four phases; address switching means for controlling the order of the read and write addresses of said plurality of pairs of frame memories so as to alternate between the pairs of frame memories; and address generating means for generating said read and write addresses of said plurality of pairs of frame memories through said address switching means.

Claim 9

An image decoder as claimed in claim 6, wherein said scanning conversion means comprises: a first plurality of demultiplexers and a second plurality of multiplexers for dividing the video signals output from said plurality of inverse quantization and inverse discrete cosine transform sections so as to be matched for the corresponding video signals output from said phase compensating means for each phase; a plurality of pairs of tri-state latches for controlling the video signals output from said second plurality of multiplexers so as to be alternately read and written with a period of a 16×16 block; a plurality of pairs of memories for alternately reading and writing the video signals under the control of respective tri-state latch among said plurality of pairs of tri-state latches; a third pair of multiplexers for alternately providing the read and write addresses to said respective pairs of memories; a counter for providing the read and write addresses of said respective pairs of memories; a latch for delay compensation; a programmable read only memory (PROM) and a PROM address counter for providing the read addresses of said respective pairs of memories to said third pair of multiplexers in order to match the orders of a memorized video signal and the video signal output from said phase compensating means; and a fourth plurality of multiplexers for alternately switching the video signals outputted from said respective pairs of memories so as to respectively provide the switched signals to said plurality of adders for each phase.

Claim 10

An image decoder as claimed in claim 6, wherein said phase compensating means comprises: a plurality of multiplexers for respectively providing the phase compensated video signals to said plurality of adders so as to be matched for the scanning order for each phase; and control signal generating means for controlling said plurality of multiplexers by regarding two lower bits of a motion vector corresponding to X axis as input control signals.

Claim 11

An image decoder as claimed in claim 6, wherein said data switching means comprises: a multiplexer for selecting the respective outputs of frame memories to be read among said respective pairs of frame memories for each phase; a pair of tri-state latches for selecting the respective input lines of frame memories to be written among said respective pairs of frame memories for each phase; and an inverter for inverting the operations of said pair of tri-state latches.