Motion image data compression system

Claim 2

A motion image data compression apparatus comprising: a first means to divide an I'th frame (I=1, 2, . . . , N-1) between the two frames F 0 and F N out of N frames (where N is an integer of 2 or more) of digital motion images, into a block B I formed of a plural number of pixels, determine the motion vector MV0I of frames F 0 and F I for each of the divided blocks B I and determine the block B 0 that uses the motion vector MV0I to predict the block B I , a second means to determine the motion vector MVNI between frames F N and F I for each block B I and use the motion vector MVNI to determine the block B N that predicts the block B I , a third means that determines the motion vector MV0N and MVN0 of frames F N and F 0 for each block B I , and uses the motion vectors MV0N and MVN0 to determine the predictive motion vector MV0I' between frames F 0 and F I , determine the block B 0 , that predicts the block B I , determine the predictive motion vector MVNI' between frames F N and F I , and uses the predictive motion vector MVNI' to determine the block B N , that predicts block B I and the block B 0N , that is the linear sum of blocks B 0 and B N , a fourth means that determines the block B DC from the average value of block B I , and a fifth means that selects the block for which the correlation with block B I is greatest, from said blocks B 0 , B N , B 0N and B DC .

Claim 3

The motion image data compression apparatus of claim 1, further comprising: a sixth means that determines the block B 0N formed by the linear sum of block B 0 and B N , with the fifth means selecting the block out of block B 0 , B N , B 0N , B 0N' and B DC for which the correlation with block B I is greatest.

Claim 4

The motion image data compression apparatus of claim 1, wherein: said fourth and fifth means and means configure a mode judgment circuit.

Claim 5

The motion image data compression apparatus of claim 3, wherein: said first means comprises a first address circuit to determine said block B 0 as first address data on the basis of the output of a first frame memory and a motion vector detection circuit, and a first work memory that stores first address data output from this circuit, said second means comprising a second address circuit to determine said block B N as second address data on the basis of the output of a second frame memory and said motion vector detection circuit, and a second work memory that stores second address data output from this circuit, said third means comprising third and fourth address generation circuits, third and fourth work memories to store third and fourth address data output from these circuits, first and second interpolation circuits that perform linear interpolation calculation of output from these third and fourth work memories, and a first adder that adds outputs of said first and second interpolation circuits, said fourth means comprising a direct current (DC) component calculation circuit provided to said mode judgment circuit and performing the DC component calculations on the basis of a fifth address data output from a fifth address generation circuit, and said fifth means comprising a minimum value judgment circuit that judges a minimum value on the basis of an output of said DC calculation circuit and address data output from said first through fourth work memories provided to said mode judgment circuit.

Claim 6

The motion image data compression apparatus of claim 4, wherein: said mode judgment circuit is provided with a first correlation calculation circuit to calculate a correlation of an output calculated by said DC calculation circuit, and second through fifth correlation circuits that calculate correlations of first through fourth data output from said first through fourth work memories.

Claim 7

The motion image data compression apparatus of claim 4, further comprising: a sixth means to determine a block B 0N formed by the linear sum of said blocks B 0 and B N , said fifth means selecting the block out of said block B 0 , B N , B 0N and B DC for which the correlation with block B I is greatest.

Claim 8

The motion image data compression apparatus of claim 6, wherein: said sixth means comprises a second adder that determines said block B 0N by adding said first and second address data output to said mode judgment circuit from said first and second work memories.

Claim 9

The motion image data compression apparatus of claim 4, wherein: predictive motion vector signals are supplied to a third and fourth address generation circuit configuring said third and fourth means, and further provided with a vector division circuit that supplies an interpolation coefficient to said first and second interpolation circuits.

Claim 10

The motion image data compression apparatus of claim 8, further comprising: a frame counter that supplies a number of frames of said motion image data to said vector division circuit, said vector division circuit being supplied with said number of frames and said motion vector detection circuit being supplied with a detected motion vector.

Claim 11

The motion image data compression apparatus of claim 1, wherein: said first means comprises a first address circuit to determine said block B 0 as first address data on the basis of the output of a first frame memory and a motion vector detection circuit, and a first work memory that stores first address data output from this circuit, said second means comprising a second address circuit to determine said block B N as second address data on the basis of the output of a second frame memory and said motion vector detection circuit, and a second work memory that stores second address data output from this circuit, said third means comprises a frame counter that counts a number of frames of said motion image signals, a vector division circuit that divides a predictive motion vector on the basis of the value counted by this counter and a motion vector (MV4I, MV0I and MV04) detected by said motion vector detection circuit, an interpolation circuit that performs interpolation calculation on the basis of an output of this division circuit and either of the outputs of said first and second work memories, and a first adder that adds outputs of said first and second interpolation circuits, said fourth means comprising a direct current (DC) component calculation circuit provided to said mode judgment circuit and performing DC component calculations on the basis of a fifth address data output from a fifth address generation circuit, and said fifth means comprising a minimum value judgment circuit that judges a minimum value on the basis of an output of said DC calculation circuit and address data output from said first, second and fifth work memories provided to said mode judgment circuit.

Claim 12

The motion image data compression apparatus of claim 10, further comprising: a sixth means that determines the block B 0N formed by the linear sum of block B 0 and B N , with the fifth means selecting the block out of block B 0 , B N , B 0N , B 0N' and B DC for which the correlation with block B I is greatest.