US5357136A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with anchored interconnection layer
Assignee: Lapis Semiconductor Co Ltd
•
Filing: 1993-04-02
•
Granted: 1994-10-18
•
Expires: 2013-04-02
Abstract
Abstract A semiconductor device having a bonding pad region, and a method of its fabrication. A conductive layer is formed on an isolation layer separating transistors of the device, to anchor the interconnection layer on the bonding region. The conductive layer may be formed from the same layer of material that gate electrodes of the transistors are formed. An oxide insulation layer covers the conductive layer and has at least one opening exposing the conductive layer in the bonding pad region. A barrier metal layer, formed on the diffusion regions and the insulation layer, extends into the opening where it makes a firm direct connection with the exposed conductive layer. A bonding pad is formed on the barrier metal layer by providing the interconnection layer on the barrier metal layer. Since the conductive layer and the barrier metal layer are firmly connected, and secures the interconnection layer in the bonding pad structure. According to a method of fabrication, the conductive layer is formed on the isolation layer simultaneously with the formation of the gate electrode, and then covered by the insulation layer. The openings are then provided in the insulation layer to expose the conductive layer. The barrier metal layer is then formed on the insulation layer so that it contacts the diffusion region and extends into the opening to become fixed to the conductive layer. The interconnection layer is then formed on the conductive layer.
Inventors
- 👤 Kentaro Yoshioka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:46
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425; H10W72/00; H10W72/90; H10W72/921; H10W72/923; H10W72/9232
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
189 words
A semiconductor device, comprising: a plurality of active regions on said semiconductor substrate, at least one of said active regions having therein and thereon a transistor, said transistor having a gate electrode; an isolation layer formed on said major surface for isolating said active regions; a conductive layer formed on said isolation layer; an insulation layer covering said conductive layer and having at least one opening exposing said conductive layer; a barrier metal layer on said insulation layer, said barrier metal layer connected to a diffusion region of said transistor, said barrier metal layer extending into said at least one opening to contact said conductive layer; and an interconnection layer formed on said barrier metal layer and electrically connected to said diffusion layer, a portion of said interconnection layer over said at least one opening and said conductive layer, said portion of said interconnection layer forming a bonding pad, wherein said insulation layer covers a portion of said isolation layer between said diffusion region and said bonding pad, said barrier metal layer and said interconnection layer extending from said conductive layer to said diffusion region on said insulation layer.
Claim 2
Dependent Claim
189 words
A semiconductor device, comprising: a plurality of active regions on said semiconductor substrate, at least one of said active regions having therein and thereon a transistor, said transistor having a gate electrode; an isolation layer formed on said major surface for isolating said active regions; a conductive layer formed on said isolation layer; an insulation layer covering said conductive layer and having at least one opening exposing said conductive layer; a barrier metal layer on said insulation layer, said barrier metal layer connected to a diffusion region of said transistor, said barrier metal layer extending into said at least one opening to contact said conductive layer; and an interconnection layer formed on said barrier metal layer and electrically connected to said diffusion layer, a portion of said interconnection layer over said at least one opening and said conductive layer, said portion of said interconnection layer forming a bonding pad, wherein said insulation layer covers a portion of said isolation layer between said diffusion region and said bonding pad, said barrier metal layer and said interconnection layer extending from said conductive layer to said diffusion region on said insulation layer.
Claim 3
Dependent Claim
30 words
A semiconductor device according to claim 1, wherein said gate electrode is formed of a gate electrode material, said conductive layer formed of the same material as said gate electrode.
Claim 4
Dependent Claim
14 words
A semiconductor device according to claim 2, wherein said insulation layer covers said transistor.
Claim 5
Dependent Claim
141 words
A semiconductor device, comprising: a semiconductor substrate; a transistor on said substrate, a bonding pad region being defined on said substrate at a location predetermined in relation to said transistor; an isolation layer on said substrate; an insulation layer on said isolation layer, said insulation layer having an opening formed therein within said bonding pad region; a barrier metal layer on said insulation layer, said barrier metal layer extending into said opening; an interconnection layer formed on said barrier metal layer, said interconnection layer electrically connected to said transistor and extending into said bonding pad region to form a bonding pad on said barrier metal layer over said opening; and an anchor layer, between said insulation layer and said isolation layer, directly beneath said of opening, said barrier metal layer directly contacting and fixed to said anchor layer through said opening.
Claim 6
Dependent Claim
141 words
A semiconductor device, comprising: a semiconductor substrate; a transistor on said substrate, a bonding pad region being defined on said substrate at a location predetermined in relation to said transistor; an isolation layer on said substrate; an insulation layer on said isolation layer, said insulation layer having an opening formed therein within said bonding pad region; a barrier metal layer on said insulation layer, said barrier metal layer extending into said opening; an interconnection layer formed on said barrier metal layer, said interconnection layer electrically connected to said transistor and extending into said bonding pad region to form a bonding pad on said barrier metal layer over said opening; and an anchor layer, between said insulation layer and said isolation layer, directly beneath said of opening, said barrier metal layer directly contacting and fixed to said anchor layer through said opening.
Claim 7
Dependent Claim
36 words
A semiconductor device according to claim 4, further comprising a protection layer over said barrier layer, said protection layer having a pad opening on said bonding pad which exposes said interconnection layer for wire lead connection.
Claim 8
Dependent Claim
23 words
A semiconductor device according to claim 4, wherein said transistor comprises a first conductive layer, said anchoring layer comprising a second conductive layer.
Claim 9
Dependent Claim
33 words
A semiconductor device according to claim 6, wherein said transistor is a MOS transistor, said first conductive layer comprising a gate electrode formed of the same material as forms said second conductive layer.
Claim 10
Dependent Claim
38 words
A semiconductor device according to claim 4, wherein said barrier metal layer fixes said interconnection layer to said conductive layer through said at least one opening, said conductive layer fixing said barrier metal layer to said isolation layer.
Claim 11
Dependent Claim
20 words
A semiconductor device according to claim 8, wherein said barrier metal layer comprises a silicide layer containing molybdenum or tungsten.
Claim 12
Dependent Claim
18 words
A semiconductor device according to claim 9, wherein said barrier metal layer further comprises a titanium nitride layer.
Claim 13
Dependent Claim
31 words
A semiconductor device according to claim 10, wherein said gate electrode and said conductive layer comprise materials selected from the group of materials consisting of polysilicon, silicide, refractory metal and polycide.
Claim 14
Dependent Claim
23 words
A semiconductor device according to claim 8, wherein said barrier metal layer has a thickness in a range of 500 to 1000 Å.
Claim 15
Dependent Claim
30 words
A semiconductor device according to claim 8, wherein said gate electrode and said conductive layer are both formed in a single layer between said insulation layer and said isolation layer.
Claim 16
Dependent Claim
36 words
A semiconductor device according to claim 8, wherein said isolation layer is formed of a field oxide, said conductive layer comprising materials selected from the group of materials consisting of polysilicon, silicide, refractory metal and polycide.
Claim 17
Dependent Claim
14 words
A semiconductor device according to claim 14, wherein said insulation layer comprises an oxide.
Claim 18
Dependent Claim
35 words
A semiconductor device according to claim 1, wherein said at least one opening comprises a plurality of openings, said barrier metal layer being fixed to said conductive layer through each of said plurality of openings.
Claim 19
Dependent Claim
31 words
A semiconductor device according to claim 1, wherein said insulation layer is an oxide, said barrier metal layer comprising a silicide layer containing molybdenum or tungsten and a titanium nitride layer.
Claim 20
Dependent Claim
26 words
A semiconductor device according to claim 1, wherein said insulation layer is an oxide, said barrier metal layer comprising titanium nitride, titanium tungsten, and tungsten layers.
Claim 21
Dependent Claim
31 words
A semiconductor layer according to claim 1, further comprising a protection layer over said barrier layer, said protection layer having a pad opening exposing said bonding pad for lead wire connection.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-17 | 1998-04-18 | 1998-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-17 | 2002-04-18 | 2002-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-17 | 2006-04-18 | 2006-10-18 | $7700.00 | Window Closed / Lapsed |