Timed make-before-break circuit for analog switch control

Claim 2

A circuit comprising: at least one delay circuit; more than one logic gate, each logic gate having one logic gate input line connected to a delay circuit input line and another logic gate input line connected to a delay circuit output line, wherein the delay circuit input line and the delay circuit output line are from the same delay circuit; and more than one switch, each switch having an input control line connected to an output line of one of the logic gates.

Claim 3

The circuit of claim 1, wherein the logic gate is an "or" gate.

Claim 4

The circuit of claim 1, wherein the logic gate is a "nand" gate.

Claim 5

The circuit of claim 1, wherein no two switches have input lines connected to an output line of the same logic gate.

Claim 6

The circuit of claim 1, wherein the delay circuit has a clock input line.

Claim 7

The circuit of claim 5, wherein the delay circuit is a flip-flop.

Claim 8

The circuit of claim 1, wherein the switches are connected to a multistate analog signal processing circuit.

Claim 9

The circuit of claim 7, wherein the multi-state analog signal processing circuit is a gain control circuit.

Claim 10

A multi-state analog signal processing circuit comprising: a make-before-break decoder; switches connected to output lines from the decoder; and a multi-state analog circuit connected to the switches through a feedback network.

Claim 11

A multi-state analog signal processing circuit comprising: a make-before-break decoder; switches connected to output lines from the decoder; and a multi-state analog circuit connected to the switches through a feedback network.

Claim 12

The circuit of claim 9, wherein the decoder is a multi-state clocked synchronous multiplexer and decoder.

Claim 13

The circuit of claim 10, wherein the decoder includes; current data input lines; delay circuits, input lines of the delay circuits connected to the current data input lines; current state inverters, inputs to the current state inverters connected to the current data input lines; last state inverters, inputs to the last state inverters connected to outputs from the delay circuits; current state logic gates, inputs to the current state logic gates connected to the current data input lines or connected to outputs from the current state inverters; last state logic gates, inputs to the last state logic gates connected to the outputs from the delay circuits or connected to outputs from the last state inverters; and output logic gates, inputs to the output logic gates connected to outputs from the current state logic gates and outputs from the last state logic gates.

Claim 14

The circuit of claim 11, wherein the current state logic gates are nand gates.

Claim 15

The circuit of claim 11, wherein the last state logic gates are nand gates.

Claim 16

The circuit of claim 13, wherein the output logic gates are nand gates.

Claim 17

The circuit of claim 14, wherein the multi-state analog circuit is a gain control circuit.

Claim 18

The circuit of claim 11, wherein each input to each current state logic gate is from a current data input line or from a current state inverter connected to the same current data input line.

Claim 19

The circuit of claim 16, wherein each input to each last state logic gate is from a delay circuit or from a last state inverter connected to the same delay circuit.

Claim 22

The method of claim 18 further comprising switching the feedback control lines of a multi-state analog circuit on and off.