US5355036A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timed make-before-break circuit for analog switch control
Assignee: Texas Instruments Inc
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Filing: 1992-11-12
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Granted: 1994-10-11
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Expires: 2012-11-12
Abstract
Abstract A timed make-before-break circuit for analog switch control is provided. The invention contains one or more delay circuit and more than one logic gate. Each logic gate has one logic gate input line connected to a delay circuit input line and another logic gate input line connected to a delay circuit output line. The logic gate input lines are connected to the delay circuit input line and the delay circuit output line from the same delay circuit. The invention also has more than one switch. Each switch has an input control line connected to a logic gate output line.
Inventors
- 👤 Daramana Gata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:45
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/002
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
83 words
A circuit comprising: at least one delay circuit; more than one logic gate, each logic gate having one logic gate input line connected to a delay circuit input line and another logic gate input line connected to a delay circuit output line, wherein the delay circuit input line and the delay circuit output line are from the same delay circuit; and more than one switch, each switch having an input control line connected to an output line of one of the logic gates.
Claim 2
Dependent Claim
83 words
A circuit comprising: at least one delay circuit; more than one logic gate, each logic gate having one logic gate input line connected to a delay circuit input line and another logic gate input line connected to a delay circuit output line, wherein the delay circuit input line and the delay circuit output line are from the same delay circuit; and more than one switch, each switch having an input control line connected to an output line of one of the logic gates.
Claim 3
Dependent Claim
13 words
The circuit of claim 1, wherein the logic gate is an "or" gate.
Claim 4
Dependent Claim
13 words
The circuit of claim 1, wherein the logic gate is a "nand" gate.
Claim 5
Dependent Claim
22 words
The circuit of claim 1, wherein no two switches have input lines connected to an output line of the same logic gate.
Claim 6
Dependent Claim
14 words
The circuit of claim 1, wherein the delay circuit has a clock input line.
Claim 7
Dependent Claim
12 words
The circuit of claim 5, wherein the delay circuit is a flip-flop.
Claim 8
Dependent Claim
17 words
The circuit of claim 1, wherein the switches are connected to a multistate analog signal processing circuit.
Claim 9
Dependent Claim
17 words
The circuit of claim 7, wherein the multi-state analog signal processing circuit is a gain control circuit.
Claim 10
Dependent Claim
31 words
A multi-state analog signal processing circuit comprising: a make-before-break decoder; switches connected to output lines from the decoder; and a multi-state analog circuit connected to the switches through a feedback network.
Claim 11
Dependent Claim
31 words
A multi-state analog signal processing circuit comprising: a make-before-break decoder; switches connected to output lines from the decoder; and a multi-state analog circuit connected to the switches through a feedback network.
Claim 12
Dependent Claim
16 words
The circuit of claim 9, wherein the decoder is a multi-state clocked synchronous multiplexer and decoder.
Claim 13
Dependent Claim
142 words
The circuit of claim 10, wherein the decoder includes; current data input lines; delay circuits, input lines of the delay circuits connected to the current data input lines; current state inverters, inputs to the current state inverters connected to the current data input lines; last state inverters, inputs to the last state inverters connected to outputs from the delay circuits; current state logic gates, inputs to the current state logic gates connected to the current data input lines or connected to outputs from the current state inverters; last state logic gates, inputs to the last state logic gates connected to the outputs from the delay circuits or connected to outputs from the last state inverters; and output logic gates, inputs to the output logic gates connected to outputs from the current state logic gates and outputs from the last state logic gates.
Claim 14
Dependent Claim
14 words
The circuit of claim 11, wherein the current state logic gates are nand gates.
Claim 15
Dependent Claim
14 words
The circuit of claim 11, wherein the last state logic gates are nand gates.
Claim 16
Dependent Claim
13 words
The circuit of claim 13, wherein the output logic gates are nand gates.
Claim 17
Dependent Claim
15 words
The circuit of claim 14, wherein the multi-state analog circuit is a gain control circuit.
Claim 18
Dependent Claim
35 words
The circuit of claim 11, wherein each input to each current state logic gate is from a current data input line or from a current state inverter connected to the same current data input line.
Claim 19
Dependent Claim
31 words
The circuit of claim 16, wherein each input to each last state logic gate is from a delay circuit or from a last state inverter connected to the same delay circuit.
Claim 20
Independent Claim
57 words
A method of controlling analog switches with a make-before-break circuit, which comprises: directing current data input signals into delay circuits; outputting last state signals from the delay circuits; directing the current data input signals and the last state signals to logic gates; outputting control signals from the logic gates; and inputting the control signals into switch circuits.
Claim 21
Independent Claim
57 words
A method of controlling analog switches with a make-before-break circuit, which comprises: directing current data input signals into delay circuits; outputting last state signals from the delay circuits; directing the current data input signals and the last state signals to logic gates; outputting control signals from the logic gates; and inputting the control signals into switch circuits.
Claim 22
Dependent Claim
20 words
The method of claim 18 further comprising switching the feedback control lines of a multi-state analog circuit on and off.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-10 | 1998-04-11 | 1998-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-10 | 2002-04-11 | 2002-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-10 | 2006-04-11 | 2006-10-11 | $7700.00 | Window Closed / Lapsed |