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US5355011A
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Insulated gate field effect transistor having LDD structure and method of making the same including a channel stop having a peak impurity concentration, the channel stop provided below a channel region
Assignee: Toshiba Corp
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Filing: 1993-07-14
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Granted: 1994-10-11
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Expires: 2013-07-14
Abstract
Abstract Insulated Gate Field Effect Transitor (IGFET) having a reduced channel length without deteriorating an electric field relief effect includes a channel stop, located below a channel region, having a peak impurity concentration. A depth of the peak impurity concentration from the substrate surface is deeper than a bottom surface of source and drain regions that provides an Lightly Doped Drain structure.
Inventors
- 👤 Osamu Takata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:24
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
136 words
A semiconductor device having an Lightly Doped Drain structure comprising: a semiconductor substrate of a first conductivity type having a surface; source and drain regions of a second conductivity type provided in said semiconductor substrate to define a channel region therebetween, one of said source and drain regions having a lightly doped region; a gate insulating film provided over said channel region; a gate electrode provided over said gate insulating film; and a channel stop of said first conductivity type, formed below said channel region, having a peak impurity concentration, a depth of said peak impurity concentration from said surface of said semiconductor substrate being deeper than a bottom surface of one of said source and drain regions, and said peak impurity concentration being increased as an effective channel length of said channel region is reduced.
Claim 2
Dependent Claim
136 words
A semiconductor device having an Lightly Doped Drain structure comprising: a semiconductor substrate of a first conductivity type having a surface; source and drain regions of a second conductivity type provided in said semiconductor substrate to define a channel region therebetween, one of said source and drain regions having a lightly doped region; a gate insulating film provided over said channel region; a gate electrode provided over said gate insulating film; and a channel stop of said first conductivity type, formed below said channel region, having a peak impurity concentration, a depth of said peak impurity concentration from said surface of said semiconductor substrate being deeper than a bottom surface of one of said source and drain regions, and said peak impurity concentration being increased as an effective channel length of said channel region is reduced.
Claim 3
Dependent Claim
19 words
The semiconductor device according to claim 1, wherein said peak impurity concentration is increased as said depth is increased.
Claim 4
Dependent Claim
25 words
The semiconductor device according to claim 1, wherein said depth of said peak impurity concentration of channel stop is deeper than said lightly doped region.
References Cited (Backward Citations)
JPH02148852A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-10 | 1998-04-11 | 1998-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-10 | 2002-04-11 | 2002-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-10 | 2006-04-11 | 2006-10-11 | $7700.00 | Window Closed / Lapsed |