US5353419A
Expired / Lapsed
US
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Memory-side driven anticipatory instruction transfer interface with processor-side instruction selection
Assignee: TRUSTEES OF UNIVERSITY OF PENNSYLVANIA A NON-PROFIT CORP OF PENNSYLVANIA
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Filing: 1992-01-09
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Granted: 1994-10-04
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Expires: 2012-01-09
Abstract
Abstract A computer architecture which significantly reduces latency in fetching instructions from main memory includes a code-pump located proximate to the memory and a filter cache located proximate to the processor. The code pump reduces latency in fetching instructions by predicting possible instruction streams that may be executed by the processor and passing instructions from all possible streams to the filter cache. The code pump fetches instructions from the memory and partially decodes the instructions to determine their types. Instruction types which may change the flow of the program such as subroutine calls and conditional branches, cause the code pump to concurrently supply instructions from all flow paths that can be predicted from these instructions. To keep track of the possible flow paths, the code pump maintains a data structure which is a combination of multiple stack entries (for call instructions) and tree entries (for branch instructions). The filter cache passes the addresses of fetched instructions back to the code pump. The code pump uses these addresses to determine which flow paths were followed and to deallocate any entries in the data structure which correspond to paths that were not followed.
Inventors
- 👤 Joseph D. Touch
- 👤 David J. Farber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:55
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3814; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F12/0875; G06F9/32; G06F9/322; G06F9/323; G06F9/3804; G06F9/3808; G06F2212/00; G06F2212/60; G06F2212/6028
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
376 words
In a computer system including a central processing unit (CPU) and a program memory wherein the CPU experiences a latency delay between requesting an instruction from the program memory and receiving the requested instruction, apparatus which reduces the latency delay comprising: instruction preprocessor means, located in proximity to the program memory, for fetching instructions for a program running on the CPU from the program memory and for providing the instructions to the CPU without any CPU driven pre-fetching, said preprocessor means comprising: instruction decoder means for assigning a type value to each of the instructions fetched from the program memory; instruction path diverger means, responsive to the type value provided by the instruction decoder means, for detecting all instructions which indicate a possible change in an execution sequence of the program and for causing the preprocessor to concurrently provide instructions from execution sequences determined from the detected instructions, the instruction path diverger means comprising: branch handling means, for detecting a conditional branch instruction and for identifying a pair of next instructions, of which pair the CPU requests one next instruction following the conditional branch instruction, and call handling means, for detecting a call instruction, and for identifying a further instruction which the CPU executes after the CPU executes a return instruction that follows the call instruction; storage means coupled to the branch handling means and call handling means for storing a plurality of indicators, the indicators identifying any of the conditional branch instruction, the pair of next instructions, the call instruction and the further instruction, that are detected by either one of the branch handling means and the call handling means; and memory access control means coupled to the storage means and the program memory for fetching from the program memory a plurality of instruction streams, and for transmitting the plurality of instruction streams without waiting to receive a request from the CPU, the plurality of instruction streams including any of the conditional branch instruction, the pair of next instructions, the call instruction and the further instruction that are identified by the indicators in the storage means; and means, responsive to instruction requests from the CPU, for selecting and providing the requested instructions to the CPU from among the instruction streams transmitted by the preprocessor means.
Claim 2
Dependent Claim
376 words
In a computer system including a central processing unit (CPU) and a program memory wherein the CPU experiences a latency delay between requesting an instruction from the program memory and receiving the requested instruction, apparatus which reduces the latency delay comprising: instruction preprocessor means, located in proximity to the program memory, for fetching instructions for a program running on the CPU from the program memory and for providing the instructions to the CPU without any CPU driven pre-fetching, said preprocessor means comprising: instruction decoder means for assigning a type value to each of the instructions fetched from the program memory; instruction path diverger means, responsive to the type value provided by the instruction decoder means, for detecting all instructions which indicate a possible change in an execution sequence of the program and for causing the preprocessor to concurrently provide instructions from execution sequences determined from the detected instructions, the instruction path diverger means comprising: branch handling means, for detecting a conditional branch instruction and for identifying a pair of next instructions, of which pair the CPU requests one next instruction following the conditional branch instruction, and call handling means, for detecting a call instruction, and for identifying a further instruction which the CPU executes after the CPU executes a return instruction that follows the call instruction; storage means coupled to the branch handling means and call handling means for storing a plurality of indicators, the indicators identifying any of the conditional branch instruction, the pair of next instructions, the call instruction and the further instruction, that are detected by either one of the branch handling means and the call handling means; and memory access control means coupled to the storage means and the program memory for fetching from the program memory a plurality of instruction streams, and for transmitting the plurality of instruction streams without waiting to receive a request from the CPU, the plurality of instruction streams including any of the conditional branch instruction, the pair of next instructions, the call instruction and the further instruction that are identified by the indicators in the storage means; and means, responsive to instruction requests from the CPU, for selecting and providing the requested instructions to the CPU from among the instruction streams transmitted by the preprocessor means.
Claim 3
Dependent Claim
74 words
Apparatus according to claim 1, wherein the instruction preprocessor means further comprises instruction path converger means, coupled to the storage means and coupled to receive data values from the CPU, for determining which instruction streams were requested and for removing from the storage means any of the plurality of indicators that identify instructions from any instruction streams which were not requested, thereby to discontinue providing instructions from said instruction streams which were not requested.
Claim 4
Dependent Claim
71 words
Apparatus according to claim 2 further comprising: cache filter means, coupled to the CPU and to the preprocessor means and located in proximity to the CPU, including: buffer means for receiving and holding instructions received from the preprocessor means for selection by the selection means; and means for sending messages to the preprocessor means indicating which instructions have been requested, wherein the selecting means is included in the cache filter means.
Claim 5
Dependent Claim
86 words
Apparatus according to claim 3 wherein: each instruction has a unique address in the program memory and the preprocessor means provides the respective instruction address from the program memory with each instruction provided to the CPU; the CPU requests each instruction using the address of the instruction in the program memory; and the selecting means compares the instruction address of each instruction provided by the preprocessor means with the address of the requested instruction from the CPU to determine if the instruction is the requested instruction.
Claim 6
Dependent Claim
47 words
Apparatus according to claim 4, wherein the storage means includes a program flow data structure, and the program flow data structure includes multiple stack data structures, each representing a respectively different call instruction combined with multiple tree data structures each representing a respectively different conditional branch instruction.
Claim 7
Dependent Claim
31 words
Apparatus according to claim 3, further comprising an additional cache memory coupled to the CPU for receiving and storing recently executed instructions that the cache filter means provide to the CPU.
Claim 8
Dependent Claim
64 words
Apparatus according to claim 1 further comprising: cache filter means, coupled to the CPU and to the preprocessor means and located in proximity to the CPU, including buffer means for receiving and holding instructions received from the preprocessor means, wherein the selecting means is included in the cache filter means, and the selecting means selects instructions from among the instructions in the buffer means.
Claim 9
Dependent Claim
261 words
In a computer system including a central processing unit (CPU) and a program memory wherein the CPU experiences a latency delay between requesting an instruction from the program memory and receiving the requested instruction, a method for reducing the latency delay comprising: fetching instructions for a program running on the CPU from the program memory; assigning a type value to each of the instructions fetched from the program memory; detecting a branch instruction and a call instruction which indicate a possible change in an execution sequence of the program based on the type value; identifying a pair of next instructions, of which pair the CPU requests one next instruction following detection of the branch instruction, and identifying a further instruction which the CPU executes after the CPU executes a return instruction that follows the call instruction; storing a plurality of indicators identifying any of the pair of next instructions, the call instruction and the further instruction that are detected into a storage medium proximate to the program memory; fetching from the program memory a plurality of instruction streams without any CPU driven pre-fetching, the plurality of instruction streams including any of the branch instruction, the pair of next instructions, the call instruction and the further instruction that are identified by the indicators in the storage medium; transmitting the fetched instruction streams without having the program memory wait to receive a request from the CPU; selecting and providing the requested instruction to the CPU from among the instruction streams transmitted by the preprocessor in response to the instruction request from the CPU.
Claim 10
Dependent Claim
261 words
In a computer system including a central processing unit (CPU) and a program memory wherein the CPU experiences a latency delay between requesting an instruction from the program memory and receiving the requested instruction, a method for reducing the latency delay comprising: fetching instructions for a program running on the CPU from the program memory; assigning a type value to each of the instructions fetched from the program memory; detecting a branch instruction and a call instruction which indicate a possible change in an execution sequence of the program based on the type value; identifying a pair of next instructions, of which pair the CPU requests one next instruction following detection of the branch instruction, and identifying a further instruction which the CPU executes after the CPU executes a return instruction that follows the call instruction; storing a plurality of indicators identifying any of the pair of next instructions, the call instruction and the further instruction that are detected into a storage medium proximate to the program memory; fetching from the program memory a plurality of instruction streams without any CPU driven pre-fetching, the plurality of instruction streams including any of the branch instruction, the pair of next instructions, the call instruction and the further instruction that are identified by the indicators in the storage medium; transmitting the fetched instruction streams without having the program memory wait to receive a request from the CPU; selecting and providing the requested instruction to the CPU from among the instruction streams transmitted by the preprocessor in response to the instruction request from the CPU.
Claim 11
Dependent Claim
48 words
A method according to claim 8, wherein the selecting step includes: receiving and holding the instructions transmitted from the program memory in a buffer located in proximity to the CPU; and selecting and providing the requested instructions to the CPU from among the instructions received by the buffer.
Claim 12
Dependent Claim
71 words
A method according to claim 9, further comprising: communicating instruction identifiers for instructions executed by the CPU; determining, from the communicated instruction identifiers, which execution sequences in the program were followed; and removing from the storage medium any of the plurality of indicators that identify instructions from any instruction streams which were not requested, thereby discontinuing the provision of instructions from the program memory for execution sequences which were not chosen.
Claim 13
Dependent Claim
71 words
A method according to claim 8, further comprising: communicating instruction identifiers for instructions executed by the CPU; determining, from the communicated instruction identifiers, which execution sequences in the program were followed; and removing from the storage medium any of the plurality of indicators that identify instructions from any instruction streams which were not requested, thereby discontinuing the provision of instructions from the program memory for execution sequences which were not chosen.
Claim 14
Dependent Claim
25 words
A method according to claim 11, further comprising storing recently executed instructions in a cache memory that were provided to the CPU from the buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |