Patent US5353120A successfully refreshed from Google Patents.
US5353120A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video field memory device for multi-broadcasting system and manufacturing method therefor
Assignee: Samsung Electronics Co Ltd
•
Filing: 1992-06-01
•
Granted: 1994-10-04
•
Expires: 2012-06-01
Abstract
Abstract A video field memory device for multi-broadcasting system employs upper and lower half memory cell arrays for storing a video signal according to the largest scanning bit and the largest scanning line of the multi-broadcasting system, and the upper and lower half memory cell arrays having the scanning bits of 1023×4 and the scanning lines of 313×4 corresponding to the largest one of various television broadcasting systems. Thus, the video field memory device for multi-broadcasting system for varying the scanning bits or the scanning lines can select a broadcasting system in a single chip by using a external TYPE signal, independent of the scanning bits or the scanning lines for each television broadcasting system.
Inventors
- 👤 Jang K. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:04
CPC Classifications
G; G06; G06F; G06F12/00; H; H04; H04N; H04N5/00; H04N5/44; H04N5/46; H04N5/76; H04N5/907; H04N7/00; H04N9/00; H04N9/79; H04N9/7921; H04N9/7925
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
175 words
A video field memory device for a multi-broadcasting system, comprising: upper and lower memory cell arrays according to a largest scanning bit and a largest scanning line for multi-broadcasting systems for storing an image memory; data write registers for writing a serial input data in parallel, said serial input data being provided through a data input buffer to a data line of said upper and lower memory cell arrays; write data pointers for assigning write bit points to said data write registers; read data registers for serially reading parallel data provided to either address line of said upper or lower half memory cell array through a data read output buffer; read data pointers for assigning read bit points to said read data registers; a line address decoder for decoding read address lines and write address lines of said upper and lower half memory cell arrays by a read address pointer, a write address pointer, and a refresh address pointer according to a predetermined sequence; and an address input circuit for controlling said respective address pointer.
Claim 2
Dependent Claim
175 words
A video field memory device for a multi-broadcasting system, comprising: upper and lower memory cell arrays according to a largest scanning bit and a largest scanning line for multi-broadcasting systems for storing an image memory; data write registers for writing a serial input data in parallel, said serial input data being provided through a data input buffer to a data line of said upper and lower memory cell arrays; write data pointers for assigning write bit points to said data write registers; read data registers for serially reading parallel data provided to either address line of said upper or lower half memory cell array through a data read output buffer; read data pointers for assigning read bit points to said read data registers; a line address decoder for decoding read address lines and write address lines of said upper and lower half memory cell arrays by a read address pointer, a write address pointer, and a refresh address pointer according to a predetermined sequence; and an address input circuit for controlling said respective address pointer.
Claim 3
Independent Claim
144 words
An apparatus for processing signals of a memory cell which is combined with a memory cell array of NTSC system and that of PAL system, comprising: a read address transferring path comprising a read address decoder for decoding read address lines according to a read block selection tag pulse and an output pulse from a read bit counter, and 568 read data registers for storing a signal selected by said read address decoder and through read input and output lines to each read address line; and a write address transferring path comprising a write address decoder for decoding write address lines according to a write address selection tag pulse and an output pulse from a write bit counter, and 568 write data registers for storing a signal selected by said address write decoder through write input and output lines at each write address line.
Claim 4
Independent Claim
144 words
An apparatus for processing signals of a memory cell which is combined with a memory cell array of NTSC system and that of PAL system, comprising: a read address transferring path comprising a read address decoder for decoding read address lines according to a read block selection tag pulse and an output pulse from a read bit counter, and 568 read data registers for storing a signal selected by said read address decoder and through read input and output lines to each read address line; and a write address transferring path comprising a write address decoder for decoding write address lines according to a write address selection tag pulse and an output pulse from a write bit counter, and 568 write data registers for storing a signal selected by said address write decoder through write input and output lines at each write address line.
Claim 5
Dependent Claim
37 words
The apparatus as claimed in claim 2, wherein a sense amplifier is connected to said pair of read input and output lines and a write driver is connected to said pair of write input and output lines.
Claim 6
Dependent Claim
39 words
The apparatus as claimed in claim 3, wherein 568 read input and output gates are connected to said read input and output lines and 568 write input and output gates are connected to said write input and output lines.
Claim 7
Dependent Claim
47 words
The apparatus as claimed in claim 2, wherein read data transfer gates are connected between said upper and lower memory cell arrays and said data read registers, and write data transfer gates are connected between said upper and lower memory cell arrays and said data write registers.
Claim 8
Dependent Claim
30 words
The apparatus as claimed in claim 2, wherein said read and write bit counters generate bit signals according to reset signals of read and write counter reset signal generators, respectively.
Claim 9
Dependent Claim
179 words
In a video field memory device having at least one memory cell array for storing an image signal of a TV broadcast system by bits and lines thereof, the improvement for multiple TV broadcasting systems: wherein the memory cell array has memory cells for a largest number of bits and lines of image signals of the multiple TV broadcasting systems; and further comprising control means for selecting memory cells of the memory cell array according to the number of bits and lines of the image signal of a selected one of the multiple TV broadcasting systems, the control means comprising resettable counter means for resetting according to the number of bits and lines of the selected one of the multiple TV broadcasting systems, the memory cell array being divided into an NTSC TV broadcasting system block and a larger PAL TV broadcasting system block, the counter means comprising means for producing a tag pulse each time the counter means is reset, and the control means selecting one of the NTSC and PAL blocks in response to each tag pulse.
Claim 10
Dependent Claim
179 words
In a video field memory device having at least one memory cell array for storing an image signal of a TV broadcast system by bits and lines thereof, the improvement for multiple TV broadcasting systems: wherein the memory cell array has memory cells for a largest number of bits and lines of image signals of the multiple TV broadcasting systems; and further comprising control means for selecting memory cells of the memory cell array according to the number of bits and lines of the image signal of a selected one of the multiple TV broadcasting systems, the control means comprising resettable counter means for resetting according to the number of bits and lines of the selected one of the multiple TV broadcasting systems, the memory cell array being divided into an NTSC TV broadcasting system block and a larger PAL TV broadcasting system block, the counter means comprising means for producing a tag pulse each time the counter means is reset, and the control means selecting one of the NTSC and PAL blocks in response to each tag pulse.
Claim 11
Dependent Claim
43 words
The device according to claim 7, wherein the control means comprises logic means responsive to a high logic type signal for setting one of an NTSC and a PAL TV broadcasting system and a low logic type signal for selecting the other thereof.
Claim 12
Dependent Claim
45 words
The device according to claim 8, wherein the logic means comprises first and second read counting reset signal generators respectively responsive to the high and low logic type signals and an OR gate for communicating responses of the reset signal generators to the counter means.
Claim 13
Dependent Claim
60 words
The device according to claim 9, wherein the tag means comprises a pulse generator for producing a generated pulse in response to each resetting of the counter means, a tag generator for producing the tag pulse in response to the generated pulse, and clear signal means for providing a clear signal that resets the tag generator after each tag pulse.
Claim 14
Dependent Claim
43 words
The device according to claim 10, wherein the memory cell array has input and output means for receiving and outputting the image signals of the multiple TV broadcasting systems and the control means are operative on each of the input and output means.
Claim 15
Dependent Claim
60 words
The device according to claim 7, wherein the tag means comprises a pulse generator for producing a generated pulse in response to each resetting of the counter means, a tag generator for producing the tag pulse in response to the generated pulse, and clear signal means for providing a clear signal that resets the tag generator after each tag pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |