Video field memory device for multi-broadcasting system and manufacturing method therefor

Claim 1

A video field memory device for a multi-broadcasting system, comprising: upper and lower memory cell arrays according to a largest scanning bit and a largest scanning line for multi-broadcasting systems for storing an image memory; data write registers for writing a serial input data in parallel, said serial input data being provided through a data input buffer to a data line of said upper and lower memory cell arrays; write data pointers for assigning write bit points to said data write registers; read data registers for serially reading parallel data provided to either address line of said upper or lower half memory cell array through a data read output buffer; read data pointers for assigning read bit points to said read data registers; a line address decoder for decoding read address lines and write address lines of said upper and lower half memory cell arrays by a read address pointer, a write address pointer, and a refresh address pointer according to a predetermined sequence; and an address input circuit for controlling said respective address pointer.

Claim 3

An apparatus for processing signals of a memory cell which is combined with a memory cell array of NTSC system and that of PAL system, comprising: a read address transferring path comprising a read address decoder for decoding read address lines according to a read block selection tag pulse and an output pulse from a read bit counter, and 568 read data registers for storing a signal selected by said read address decoder and through read input and output lines to each read address line; and a write address transferring path comprising a write address decoder for decoding write address lines according to a write address selection tag pulse and an output pulse from a write bit counter, and 568 write data registers for storing a signal selected by said address write decoder through write input and output lines at each write address line.

Claim 4

An apparatus for processing signals of a memory cell which is combined with a memory cell array of NTSC system and that of PAL system, comprising: a read address transferring path comprising a read address decoder for decoding read address lines according to a read block selection tag pulse and an output pulse from a read bit counter, and 568 read data registers for storing a signal selected by said read address decoder and through read input and output lines to each read address line; and a write address transferring path comprising a write address decoder for decoding write address lines according to a write address selection tag pulse and an output pulse from a write bit counter, and 568 write data registers for storing a signal selected by said address write decoder through write input and output lines at each write address line.