US5352989A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low input resistance amplifier stage
Assignee: Elantec Semiconductor LLC
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Filing: 1993-05-11
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Granted: 1994-10-04
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Expires: 2013-05-11
Abstract
Abstract An amplifier stage suitable for current conveyors and current mode feedback operational amplifiers has low input resistance and operates at low power. The amplifier stage comprises a buffer having inverting and non-inverting inputs and a pair of current outputs, and a pair of multiple output current mirrors which operate in conjunction with the buffer to generate an output current at a high gain node in response to an input signal applied to the buffer inputs. Each multiple output current mirror has a low impedance current input for receiving current signals generated by the buffer and multiple high impedance current outputs for providing current feedback to the inverting input of the buffer and output current to the high gain node of the amplifier stage. The magnitudes of the feedback and output currents are determined by the resistances of current scaling resistors associated with the low impedance current input and each of the high impedance current outputs.
Inventors
- 👤 Christofer Toumazou
- 👤 Martin Anding
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:46
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H03F3/3001; H03F3/3069
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
271 words
A low input resistance amplifier stage comprising: a buffer having inverting and non-inverting inputs and a pair of current outputs, for generating current signals at the current outputs in response to a differential signal applied between the inverting and non-inverting inputs; and a pair of multiple output current mirrors, each multiple output current mirror comprising: a first transistor having a base, collector and emitter, the emitter being connected to a supply voltage through a first current scaling resistor, and the collector being connected to one of the current outputs of the buffer to form a low impedance input for the current mirror; a second transistor having a base, collector and emitter, the emitter being connected to the supply voltage through a second current scaling resistor and the collector being connected to the inverting input of the buffer through a first isolating transistor to form a high impedance output of the current mirror for providing a feedback current to the inverting input, depending on the ratio of the resistances of the first and second current scaling resistors; and a third transistor having a base, collector and emitter, the emitter being connected to the supply voltage through a third current scaling resistor, the base being connected to the bases of the first and second transistors, and the collector being connected to the base and to a high gain node of the amplifier stage through a second isolating transistor to form a high impedance output of the current mirror for providing an output current to the high gain node, depending on the ratio of the resistances of the first and third current scaling resistors.
Claim 2
Dependent Claim
271 words
A low input resistance amplifier stage comprising: a buffer having inverting and non-inverting inputs and a pair of current outputs, for generating current signals at the current outputs in response to a differential signal applied between the inverting and non-inverting inputs; and a pair of multiple output current mirrors, each multiple output current mirror comprising: a first transistor having a base, collector and emitter, the emitter being connected to a supply voltage through a first current scaling resistor, and the collector being connected to one of the current outputs of the buffer to form a low impedance input for the current mirror; a second transistor having a base, collector and emitter, the emitter being connected to the supply voltage through a second current scaling resistor and the collector being connected to the inverting input of the buffer through a first isolating transistor to form a high impedance output of the current mirror for providing a feedback current to the inverting input, depending on the ratio of the resistances of the first and second current scaling resistors; and a third transistor having a base, collector and emitter, the emitter being connected to the supply voltage through a third current scaling resistor, the base being connected to the bases of the first and second transistors, and the collector being connected to the base and to a high gain node of the amplifier stage through a second isolating transistor to form a high impedance output of the current mirror for providing an output current to the high gain node, depending on the ratio of the resistances of the first and third current scaling resistors.
Claim 3
Dependent Claim
55 words
A low input resistance amplifier stage in accordance with claim 1, wherein the ratio of the resistances of the first and second current scaling resistors is K:1 and K is less than 1, and the ratio of the resistances of the first and third current scaling resistors is K:N and N is at least 1.
Claim 4
Dependent Claim
25 words
A low input resistance amplifier stage in accordance with claim 2, wherein K is between 0.1 and 1 and N is between 1 and 3.
Claim 5
Dependent Claim
78 words
A low input resistance amplifier stage in accordance with claim 1, wherein each of the multiple output current mirrors includes a fourth transistor having a base, collector and emitter, the emitter being connected to the supply voltage through a fourth current scaling resistor, the collector being connected to the high gain node through a third isolating transistor, and the base being connected to the base of the third transistor, for providing additional current to the high gain node.
Claim 6
Dependent Claim
30 words
A low input resistance amplifier stage in accordance with claim 4, wherein the resistances of the first, second, third, and fourth current scaling resistors are in the ratio of K:1:1:K.
Claim 7
Dependent Claim
56 words
A low input resistance amplifier stage in accordance with claim 4, wherein a current source is connected between each of the current outputs of the buffer and the corresponding supply voltage, for diverting a preselected amount of the current signal generated by the buffer from the collector of the first transistor of the corresponding current mirror.
Claim 8
Dependent Claim
56 words
A low input resistance amplifier stage in accordance with claim 1, wherein a current source is connected between each of the current outputs of the buffer and the corresponding supply voltage, for diverting a preselected amount of the current signal generated by the buffer from the collector of the first transistor of the corresponding current mirror.
References Cited (Backward Citations)
US5103188A
Cited
US5179355A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |