Buffered transconductance amplifier

Claim 2

An electrical circuit for amplifying complex or high speed signals, constructed with solid state devices, comprising: a first input buffer, having a single, non-inverting input of high impedance, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer for supplying currents to said first buffer's low impedance output; a pair of opposing current mirrors whose inputs are connected to said first current rail of said first input buffer and whose outputs are combined together; a load resistor connected to output of said first input buffer, the combination of said first buffer, said opposing current mirrors and said load resistor forming a first input stage; a second output buffer having a single non-inverting input of high impedance which is connected to the output of the opposing current mirrors, an open loop voltage gain not exceeding unity, and a low impedance output; a second current rail traversing through said second output buffer for supplying currents to said second buffers low impedance output; dual voltage supply rails for driving said opposing current mirrors, subsequent first input buffer and said second output buffer; and, a feedback means is connected from the said second buffer output to the load resistor of said input buffer.

Claim 3

An electrical circuit as defined in claim 1 with wherein a feedback network means is connected from a final output to the inputs of said opposing current mirrors.

Claim 4

An electrical circuit as defined in claim 1 with bias means to minimize or eliminate common crossover distortion.

Claim 5

An electrcial circuit as defined in claim 1 for use at different power levels wherein said amplifier circuits are designed and used for very low power signals, low and medium power signals, as well as high and very high power signals of complex, wideband wave shapes.

Claim 6

An electrical circuit as defined in claim 1 wherein said amplifier circuits are designed and used for audio signals, at any or all appropriate power levels used therein.

Claim 7

An electrical circuit as defined in claim 1 wherein said amplifier circuits are designed and used for servo control loop signals, at any or all appropriate power levels used therein.

Claim 8

An electrical circuit as defined in claim 1 wherein said amplifier circuits are designed and used for robotic control loop signals at any or all appropriate power levels used therein.

Claim 9

An electrical circuit with very high gain for amplifying complex or high speed signals constructed with solid state devices, comprising: a first input buffer, having a single, non-inverting input of high impedance, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer for supplying currents to said first buffer's low impedance output; a pair of opposing current mirrors whose inputs are connected to said first current rail of said first input buffer and whose outputs are combined together; a load resistor connected to output of said first input buffer, the combination of said first buffer, said opposing current mirrors and said load resistor forming a first input stage; a second input stage, similar in form and function to said first input stage, wherein the input of said second input stage is connected to the combined outputs of the opposing current mirrors of said first input stage; a third output buffer having a single, non-inverting input and a low impedance output and transversing current rail is attached to the combined current mirror outputs of said second input stage; dual voltage supply rails for driving said first and second input stages and said third output buffer; and feedback means connecting a final output to the load resistors of at least one of said first and second input stages.

Claim 10

An electrical circuit with very high gain for amplifying complex or high speed signals constructed with solid state devices, comprising: a first input buffer, having a single, non-inverting input of high impedance, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer for supplying currents to said first buffer's low impedance output; a pair of opposing current mirrors whose inputs are connected to said first current rail of said first input buffer and whose outputs are combined together; a load resistor connected to output of said first input buffer, the combination of said first buffer, said opposing current mirrors and said load resistor forming a first input stage; a second input stage, similar in form and function to said first input stage, wherein the input of said second input stage is connected to the combined outputs of the opposing current mirrors of said first input stage; a third output buffer having a single, non-inverting input and a low impedance output and transversing current rail is attached to the combined current mirror outputs of said second input stage; dual voltage supply rails for driving said first and second input stages and said third output buffer; and feedback means connecting a final output to the load resistors of at least one of said first and second input stages.

Claim 11

An electrical circuit as defined in claim 8, wherein a feedback network means is connected from a final output to at least one pair of inputs of said opposing current mirrors.

Claim 12

An electrical circuit as defined in claim 8 with bias means to minimize or eliminate common crossover distortion.

Claim 13

An electrical circuit as defined in claim 8 for use at different power levels wherein said amplifier circuits are designed and used for very low power signals, low and medium power signals, as well as high and very high power signals of complex, wideband wave shapes.

Claim 14

An electrical circuit as defined in claim 8 wherein said amplifier circuits are designed and used for audio signals, at any or all appropriate power levels used therein.

Claim 15

An electrical circuit as defined in claim 8 wherein said amplifier circuits are designed and used for servo control loop signals, at any or all appropriate power levels used therein.

Claim 16

An electrical circuit as defined in claim 8 wherein said amplifier circuits are designed and used for robotic control loop signals at any or all appropriate power levels used therein.

Claim 21

An electrical circuit for amplifying complex, high speed power signals, having voltage regulation for the input stage, and constructed with solid state devices, comprising: a first input buffer, having a single, non-inverting input of high impedance, an open loop voltage gain not exceeding unity, and a low inpedance output; a first current rail traversing through said first input buffer for supplying currents to said first buffer's low inpedance output; a pair of opposing current mirrors whose inputs are connected to said first current rail of said first input buffer and whose outputs are combined together; a load resistor connected to output of said first input buffer, the combination of said first buffer, said opposing current mirrors and said load resistor forming a first input stage; a first set of dual, regulated, opposing voltage supply rails for supplying currents to said first input stage; a second output buffer having a single, non-inverting input of high impedance which is connected to the combined outputs of the said opposing current mirrors, an open loop voltage gain not exceeding unity, and a low impedance output; a second current rail traversing through said second output buffer for supplying current to said second buffer's low impedance output; a second, higher set of dual, opposing voltage supply rails for supplying currents to both said current rail of said output buffer and the inputs of the said first set of regulated voltage supply rails; and, a feedback means is connected from the said second buffer's output to the load resistor of said first input buffer.

Claim 22

An electrical circuit for amplifying complex, high speed power signals, having voltage regulation for the input stage, and constructed with solid state devices, comprising: a first input buffer, having a single, non-inverting input of high impedance, an open loop voltage gain not exceeding unity, and a low inpedance output; a first current rail traversing through said first input buffer for supplying currents to said first buffer's low inpedance output; a pair of opposing current mirrors whose inputs are connected to said first current rail of said first input buffer and whose outputs are combined together; a load resistor connected to output of said first input buffer, the combination of said first buffer, said opposing current mirrors and said load resistor forming a first input stage; a first set of dual, regulated, opposing voltage supply rails for supplying currents to said first input stage; a second output buffer having a single, non-inverting input of high impedance which is connected to the combined outputs of the said opposing current mirrors, an open loop voltage gain not exceeding unity, and a low impedance output; a second current rail traversing through said second output buffer for supplying current to said second buffer's low impedance output; a second, higher set of dual, opposing voltage supply rails for supplying currents to both said current rail of said output buffer and the inputs of the said first set of regulated voltage supply rails; and, a feedback means is connected from the said second buffer's output to the load resistor of said first input buffer.

Claim 23

An electrical circuit as defined in claim 17 with bias means to minimize or eliminate common crossover distortion.

Claim 24

An electrical circuit as defined in claim 17 for use at different power levels wherein said amplifier circuits are designed and used for very low power signals, low and medium power signals, as well as high and very high power signals of complex, wideband wave shapes.

Claim 25

An electrical circuit as defined in claim 17 wherein said amplifier circuits are designed and used for audio signals, at any or all appropriate power levels used therein.

Claim 26

An electrical circuit as defined in claim 17 wherein said amplifier circuits are designed and used for servo control loop signals, at any or all appropriate power levels used therein.

Claim 27

An electrical circuit as defined in claim 17 wherein said amplifier circuits are designed and used for robotic control loop signals at any or all appropriate power levels used therein.

Claim 28

An electrical circuit for amplifying complex, high speed, high voltage signals having voltage regulation for the input buffer and constructed with solid state devices, comprising: a first input buffer, having a single, non-inverting input of high impedance, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer for supplying currents to said first buffer's low impedance output; a first set of dual, regulated, opposing voltage supply rails for supplying currents to said current rail of said first input buffer; a pair of opposing current mirrors, whose inputs supply currents to the said first set of regulated voltage supply rails, and whose outputs are combined together; a load resistor connected to output of said first input buffer, the combination of said first buffer, said first set of regulated voltage supply rails, said opposing current mirrors, and said load resistor forming a first input stage; a second output buffer having a single, non-inverting input of high impedance which is connected to the combined outputs of the said opposing current mirrors, an open loop voltage gain not exceeding unity, and a low impedance output; a second current rail traversing through said second output buffer for supplying currents to said second buffer's low impedance output; a second set of dual, opposing high voltage supply rails for supplying currents to said first input stage and said current rail of said output buffer; and, a feedback means is connected from the said second buffer's output to the load resistor of said first input buffer.

Claim 29

An electrical circuit for amplifying complex, high speed, high voltage signals having voltage regulation for the input buffer and constructed with solid state devices, comprising: a first input buffer, having a single, non-inverting input of high impedance, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer for supplying currents to said first buffer's low impedance output; a first set of dual, regulated, opposing voltage supply rails for supplying currents to said current rail of said first input buffer; a pair of opposing current mirrors, whose inputs supply currents to the said first set of regulated voltage supply rails, and whose outputs are combined together; a load resistor connected to output of said first input buffer, the combination of said first buffer, said first set of regulated voltage supply rails, said opposing current mirrors, and said load resistor forming a first input stage; a second output buffer having a single, non-inverting input of high impedance which is connected to the combined outputs of the said opposing current mirrors, an open loop voltage gain not exceeding unity, and a low impedance output; a second current rail traversing through said second output buffer for supplying currents to said second buffer's low impedance output; a second set of dual, opposing high voltage supply rails for supplying currents to said first input stage and said current rail of said output buffer; and, a feedback means is connected from the said second buffer's output to the load resistor of said first input buffer.

Claim 30

An electrical circuit as defined in claim 23 with bias means to minimize or eliminate common crossover distortion.

Claim 31

An electrical circuit as defined in claim 23 for use at different power levels wherein said amplifier circuits are designed and used for very low power signals, low and medium power signals, as well as high and very high power signals of complex, wideband wave shapes.

Claim 32

An electrical circuit as defined in claim 23 wherein said amplifier circuits are designed and used for audio signals, at any or all appropriate power levels used therein.

Claim 33

An electrical circuit as defined in claim 23 wherein said amplifier circuits are designed and used for servo control loop signals, at any or all appropriate power levels used therein.

Claim 34

An electrical circuit as defined in claim 23 wherein said amplifier circuits are designed and used for robotic control loop signals at any or all appropriate power levels used therein.

Claim 35

An electrical circuit for amplifying complex, high speed signals having extremely high gain and constructed with solid state devices, wherein a plurality of input stages are connected in a serial fashion or cascaded to form a continuous chain, comprising: a first input buffer, having a single, non-inverting input of high impedance, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer for supplying currents to said first buffer's low impedance output; a pair of opposing current mirrors whose inputs are connected to said first current rail of said first input buffer and whose outputs are combined together; a load resistor connected to output of said first input buffer, the combination of said first buffer, said opposing current mirrors and said load resistor forming a first input stage; a plurality of input stages, similar in form and function to said first input stage, are connected in a serially cascaded fashion, buffer input to current mirror output, starting with the said first input stage and continuing until the last input stage; a final output buffer having a single non-inverting input of high impedance which is connected to the combined outputs of the last set of opposing current mirrors, an open loop voltage gain not exceeding unity, and a low impedance output; a current rail traversing through said final output buffer for supplying currents to said final buffer's low impedance output; a set of dual, opposing voltage supply rails for supplying currents to all said input stages and said current rail of said output buffer; and, a feedback network means is connected from a final output to the load resistors of at least one of said input buffers and to at least one pair of the inputs of said opposing current mirrors.

Claim 36

An electrical circuit for amplifying complex, high speed signals having extremely high gain and constructed with solid state devices, wherein a plurality of input stages are connected in a serial fashion or cascaded to form a continuous chain, comprising: a first input buffer, having a single, non-inverting input of high impedance, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer for supplying currents to said first buffer's low impedance output; a pair of opposing current mirrors whose inputs are connected to said first current rail of said first input buffer and whose outputs are combined together; a load resistor connected to output of said first input buffer, the combination of said first buffer, said opposing current mirrors and said load resistor forming a first input stage; a plurality of input stages, similar in form and function to said first input stage, are connected in a serially cascaded fashion, buffer input to current mirror output, starting with the said first input stage and continuing until the last input stage; a final output buffer having a single non-inverting input of high impedance which is connected to the combined outputs of the last set of opposing current mirrors, an open loop voltage gain not exceeding unity, and a low impedance output; a current rail traversing through said final output buffer for supplying currents to said final buffer's low impedance output; a set of dual, opposing voltage supply rails for supplying currents to all said input stages and said current rail of said output buffer; and, a feedback network means is connected from a final output to the load resistors of at least one of said input buffers and to at least one pair of the inputs of said opposing current mirrors.

Claim 37

An electrical circuit as defined in claim 29 with bias means to minimize or eliminate common crossover distortion.

Claim 38

An electrical circuit as defined in claim 29 for use at different power levels wherein said amplifier circuits are designed and used for very low power signals, low and medium power signals, as well as high and very high power signals of complex, wideband wave shapes.

Claim 39

An electrical circuit as defined in claim 29 wherein said amplifier circuits are designed and used for audio signals, at any or all appropriate power levels used therein.

Claim 40

An electrical circuit as defined in claim 29 wherein said amplifier circuits are designed and used for servo control loop signals, at any or all appropriate power levels used therein.

Claim 41

An electrical circuit as defined in claim 29 wherein said amplifier circuits are designed and used for robotic control loop signals at any or all appropriate power levels used therein.

Claim 42

An electrical circuit for amplifying the difference between complex, high speed signals having differential outputs and constructed with solid state devices, comprising: a first and second input buffer, each having a single non-inverting high impedance input, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer, a second current rail traversing through said second input buffer, each current rail for supplying currents to said respective first and second buffers' low impedance outputs; a load resistor means is connected between the outputs of said first and second input buffers, the combination of said first input buffer, said second input buffer, and said load resistor forming a differential buffer block; a first and second pair of opposing current mirrors each with combined outputs and whose inputs are connected to said first current rail of said first input buffer and to said second current rail of said second input buffer, respectively; a first and second output buffer, each having a single, non-inverting high impedance input which are each connected respectively to the combined outputs of said first and second opposing current mirrors, each having open loop voltage gains not exceeding unity, and each having low impedance outputs; a first current rail traversing through said first output buffer, a second current rail traversing through said second output buffer, each current rail for supplying currents to said respective first and second output buffers' low impedance outputs; dual opposing voltage supply rails for driving both said opposing current mirrors, subsequent first and second input buffers and said first and second output buffers; and a feedback network means of passive components is connected from at least one output of said first and second output buffers to at least one end of the load resistor means.

Claim 43

An electrical circuit for amplifying the difference between complex, high speed signals having differential outputs and constructed with solid state devices, comprising: a first and second input buffer, each having a single non-inverting high impedance input, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer, a second current rail traversing through said second input buffer, each current rail for supplying currents to said respective first and second buffers' low impedance outputs; a load resistor means is connected between the outputs of said first and second input buffers, the combination of said first input buffer, said second input buffer, and said load resistor forming a differential buffer block; a first and second pair of opposing current mirrors each with combined outputs and whose inputs are connected to said first current rail of said first input buffer and to said second current rail of said second input buffer, respectively; a first and second output buffer, each having a single, non-inverting high impedance input which are each connected respectively to the combined outputs of said first and second opposing current mirrors, each having open loop voltage gains not exceeding unity, and each having low impedance outputs; a first current rail traversing through said first output buffer, a second current rail traversing through said second output buffer, each current rail for supplying currents to said respective first and second output buffers' low impedance outputs; dual opposing voltage supply rails for driving both said opposing current mirrors, subsequent first and second input buffers and said first and second output buffers; and a feedback network means of passive components is connected from at least one output of said first and second output buffers to at least one end of the load resistor means.

Claim 44

An electrical circuit as defined in claim 35 with bias means to minimize or eliminate common crossover distortion.

Claim 45

An electrical circuit as defined in claim 35 for use at different power levels wherein said amplifier circuits are designed and used for very low power signals, low and medium power signals, as well as high and very high power signals of complex, wideband wave shapes.

Claim 46

An electrical circuit as defined in claim 35 wherein said amplifier circuits are designed and used for audio signals, at any or all appropriate power levels used therein.

Claim 47

An electrical circuit as defined in claim 35 wherein said amplifier circuits are designed and used for servo control loop signals, at any or all appropriate power levels used therein.

Claim 48

An electrical circuit as defined in claim 35 wherein said amplifier circuits are designed and used for robotic control loop signals at any or all appropriate power levels used therein.

Claim 49

An electrical circuit for amplifying the difference between complex, high speed signals having differential outputs, having voltage regulation for the gain stage, and constructed with solid state devices, comprising: a first and second input buffer, each having a single non-inverting high impedance input, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer, a second current rail traversing through said second input buffer, each current rail for supplying currents to said respective first and second input buffers' low impedance outputs; a load resistor means is connected between the outputs of said first and second input buffers, the combination of said first input buffer, said second input buffer, and said load resistor forming a differential buffer block; a first and second pair of opposing current mirrors with combined outputs and whose inputs are connected to said first current rail of said first input buffer and to said second current rail of said second input buffer, respectively; a first set of dual, regulated, opposing voltage supply rails for supplying currents to said first and second opposing current mirrors and subsequent said differential buffer block; a first and second output buffer, each having a single non-inverting high impedance input which is connected respectively each to the combined output of said first and second opposing current mirrors, each having an open loop voltage gain not exceeding unity, and each having a low impedance output; a first current rail traversing through said first output buffer, a second current rail traversing through said second output buffer, each current rail for supplying currents to said first and second output buffers' low impedance outputs; a second, higher set of dual, opposing voltage supply rails for supplying currents to both said current rails of said output buffers, and the inputs of the said first set of regulated voltage supply rails; and, a feedback network means of passive components is connected from at least one output of said first and second output buffers to at least one end of the load resistor means.

Claim 50

An electrical circuit for amplifying the difference between complex, high speed signals having differential outputs, having voltage regulation for the gain stage, and constructed with solid state devices, comprising: a first and second input buffer, each having a single non-inverting high impedance input, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer, a second current rail traversing through said second input buffer, each current rail for supplying currents to said respective first and second input buffers' low impedance outputs; a load resistor means is connected between the outputs of said first and second input buffers, the combination of said first input buffer, said second input buffer, and said load resistor forming a differential buffer block; a first and second pair of opposing current mirrors with combined outputs and whose inputs are connected to said first current rail of said first input buffer and to said second current rail of said second input buffer, respectively; a first set of dual, regulated, opposing voltage supply rails for supplying currents to said first and second opposing current mirrors and subsequent said differential buffer block; a first and second output buffer, each having a single non-inverting high impedance input which is connected respectively each to the combined output of said first and second opposing current mirrors, each having an open loop voltage gain not exceeding unity, and each having a low impedance output; a first current rail traversing through said first output buffer, a second current rail traversing through said second output buffer, each current rail for supplying currents to said first and second output buffers' low impedance outputs; a second, higher set of dual, opposing voltage supply rails for supplying currents to both said current rails of said output buffers, and the inputs of the said first set of regulated voltage supply rails; and, a feedback network means of passive components is connected from at least one output of said first and second output buffers to at least one end of the load resistor means.

Claim 51

An electrical circuit as defined in claim 41 with with bias means to minimize or eliminate common crossover distortion.

Claim 52

An electrical circuit as defined in claim 41 for use at different power levels wherein said amplifier circuits are designed and used for very low power signals, low and medium power signals, as well as high and very high power signals of complex, wideband wave shapes.

Claim 53

An electrical circuit as defined in claim 41 wherein said amplifier circuits are designed and used for audio signals, at any or all appropriate power levels used therein.

Claim 54

An electrical circuit as defined in claim 41 wherein said amplifier circuits are designed and used for servo control loop signals, at any or all appropriate power levels used therein.

Claim 55

An electrical circuit as defined in claim 41 wherein said amplifier circuits are designed and used for robotic control loop signals at any or all appropriate power levels used therein.

Claim 56

An electrical circuit for amplifying complex, high speed, high power signals having voltage regulation for the input buffer and the input stage, and constructed with solid state devices, comprising: a first input buffer, having a single, non-inverting input of high impedance, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer for supplying currents to said first buffer's low impedance output; a first set of dual, regulated, opposing voltage supply rails for supplying currents to said current rail of said first input buffer; a pair of opposing current mirrors, whose inputs supply currents to the said first set of regulated voltage supply rails, and whose outputs are combined together; a load resistor connected to output of said first input buffer, the combination of said first buffer, said first set of regulated voltage supply rails, said opposing current mirrors, and said load resistor forming a first input stage; a second set of dual, regulated, opposing high voltage supply rails for supplying currents to said first input stage; a second output buffer having a single, non-inverting input of high impedance which is connected to the combined outputs of the said opposing current mirrors, an open loop voltage gain not exceeding unity, and a low impedance output; a second current rail traversing through said second output buffer for supplying currents to said second buffer's low impedance output; a third, higher set of dual, opposing high voltage supply rails for supplying currents to both said current rail of said output buffer and the inputs of the said second set of regulated high voltage supply rails; and, a feedback means is connected from the said second buffer's output to the load resistor of said first input buffer.

Claim 57

An electrical circuit for amplifying complex, high speed, high power signals having voltage regulation for the input buffer and the input stage, and constructed with solid state devices, comprising: a first input buffer, having a single, non-inverting input of high impedance, an open loop voltage gain not exceeding unity, and a low impedance output; a first current rail traversing through said first input buffer for supplying currents to said first buffer's low impedance output; a first set of dual, regulated, opposing voltage supply rails for supplying currents to said current rail of said first input buffer; a pair of opposing current mirrors, whose inputs supply currents to the said first set of regulated voltage supply rails, and whose outputs are combined together; a load resistor connected to output of said first input buffer, the combination of said first buffer, said first set of regulated voltage supply rails, said opposing current mirrors, and said load resistor forming a first input stage; a second set of dual, regulated, opposing high voltage supply rails for supplying currents to said first input stage; a second output buffer having a single, non-inverting input of high impedance which is connected to the combined outputs of the said opposing current mirrors, an open loop voltage gain not exceeding unity, and a low impedance output; a second current rail traversing through said second output buffer for supplying currents to said second buffer's low impedance output; a third, higher set of dual, opposing high voltage supply rails for supplying currents to both said current rail of said output buffer and the inputs of the said second set of regulated high voltage supply rails; and, a feedback means is connected from the said second buffer's output to the load resistor of said first input buffer.

Claim 58

An electrical circuit as defined in claim 47 with bias means to minimize or eliminate common crossover distortion.

Claim 59

An electrical circuit as defined in claim 47 for use at different power levels wherein said amplifier circuits are designed and used for very low power signals, low and medium power signals, as well as high and very high power signals of complex, wideband wave shapes.

Claim 60

An electrical circuit as defined in claim 47 wherein said amplifier circuits are designed and used for audio signals, at any or all appropriate power levels used therein.

Claim 61

An electrical circuit as defined in claim 47 wherein said amplifier circuits are designed and used for servo control loop signals, at any or all appropriate power levels used therein.

Claim 62

An electrical circuit as defined in claim 47 wherein said amplifier circuits are designed and used for robotic control loop signals at any or all appropriate power levels used therein.