Patent US5352987A successfully refreshed from Google Patents.
US5352987A
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Analog multiplexer
Assignee: Elantec Semiconductor LLC
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Filing: 1993-07-21
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Granted: 1994-10-04
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Expires: 2013-07-21
Abstract
Abstract An analog multiplier includes a plurality of input stages that are selectively coupled to inputs of a common amplifier through coupling elements and logic circuitry that selectively controls conduction through the coupling elements to the amplifier. The coupling elements include transistors that are common base connected to a bias supply for shunting capacitive feed through to the amplifier.
Inventors
- 👤 Barry Harvey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:56
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6257; H03K17/6264
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
169 words
An analog multiplexer comprising: an amplifier including a pair of inputs for forming an output from signals appearing on the pair of inputs thereof; a plurality of input stages, each including a pair of transistors of one conductivity type having bases and collectors and having emitters commonly connected to receive bias signal; logic means including emitter followers of the one conductivity type with emitters connected to the collectors of the transistors in each of the input stages for selectively shunting collector currents therethrough in response to applied logic signals; and a coupling transistor of the one conductivity type stage, each coupling transistor having an emitter connected to the collector of each transistor in each of the input stages, and having a collector connected to one of the pair of inputs of the amplifier, and having a base connected to a source of bias signal for selectively conducting signal through the coupling transistors to the inputs of the amplifier in response to the associated logic means not conducting signal therethrough.
Claim 2
Dependent Claim
169 words
An analog multiplexer comprising: an amplifier including a pair of inputs for forming an output from signals appearing on the pair of inputs thereof; a plurality of input stages, each including a pair of transistors of one conductivity type having bases and collectors and having emitters commonly connected to receive bias signal; logic means including emitter followers of the one conductivity type with emitters connected to the collectors of the transistors in each of the input stages for selectively shunting collector currents therethrough in response to applied logic signals; and a coupling transistor of the one conductivity type stage, each coupling transistor having an emitter connected to the collector of each transistor in each of the input stages, and having a collector connected to one of the pair of inputs of the amplifier, and having a base connected to a source of bias signal for selectively conducting signal through the coupling transistors to the inputs of the amplifier in response to the associated logic means not conducting signal therethrough.
References Cited (Backward Citations)
JPH04170814A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |