Reduced power line fluctuation/noise circuit by increasing impedance level when number of bus lines simultaneously change state exceeds the predetermined number

Claim 2

A circuit in a microcomputer for reducing noise on a power line created when selected ones of a plurality of bus lines connected to an external load simultaneously change state, said circuit comprising: a plurality of variable-impedance buffer units, coupled to the plurality of bus lines, for driving signals between the plurality of bus lines and the external load, said plurality of variable impedance buffer units having a specific impedance level; a detector circuit, coupled to the plurality of bus lines, for detecting signal inversions in each one of the plurality of bus lines; and a decoder, coupled to said detector circuit and to said plurality of variable-impedance buffer units, for increasing said impedance level of said plurality of variable-impedance buffer units when the number of bus lines in which said detector circuit detects signal inversions exceeds a predetermined number, thereby decreasing through current of said buffer units and reducing noise on the power line.

Claim 3

The circuit set forth in claim 1 wherein said decoder allows said predetermined number to be changed.

Claim 4

The circuit set forth in claim 1 wherein each of said plurality of variable-impedance buffers comprise first and second buffers coupled in parallel, wherein said first buffer is disabled and disconnected from said second buffer by the output of the said decoder.

Claim 5

A single-chip microcomputer that stores data in an external memory and generates address signals to access the external memory, said microcomputer comprising: a central processing unit for generating said address signals; a plurality of address bus lines coupled to said central processing unit for transmitting said address signals; an output buffer circuit, coupled to said plurality of address bus lines, for driving said address signals to the external memory, said output buffer circuit introducing an impedance level on said plurality of address bus lines; a detector circuit, coupled to said plurality of address bus lines, for detecting how many of said address bus lines change state at a predetermined time; impedance varying means, coupled to said detector circuit and to said output buffer circuit, for increasing said impedance introduced by said output buffer circuit when the number of address bus lines that change state at said predetermined time is greater than a predetermined number so that through current of said output buffer circuit is reduced and power line fluctuation associated with said through current is reduced.

Claim 6

A single-chip microcomputer that stores data in an external memory and generates address signals to access the external memory, said microcomputer comprising: a central processing unit for generating said address signals; a plurality of address bus lines coupled to said central processing unit for transmitting said address signals; an output buffer circuit, coupled to said plurality of address bus lines, for driving said address signals to the external memory, said output buffer circuit introducing an impedance level on said plurality of address bus lines; a detector circuit, coupled to said plurality of address bus lines, for detecting how many of said address bus lines change state at a predetermined time; impedance varying means, coupled to said detector circuit and to said output buffer circuit, for increasing said impedance introduced by said output buffer circuit when the number of address bus lines that change state at said predetermined time is greater than a predetermined number so that through current of said output buffer circuit is reduced and power line fluctuation associated with said through current is reduced.

Claim 7

The microcomputer of claim 4 wherein said predetermined number can be varied by said impedance varying means.

Claim 8

The microcomputer of claim 5 wherein said output buffer circuit comprises a first and second buffer gate coupled in parallel for each address bus line and wherein said impedance varying means increases the impedance of said output buffer circuit by disabling each first buffer gate.

Claim 9

The microcomputer of claim 6 wherein each one of said first buffer gates comprises a tri-state gate.