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Patent US5349309A successfully refreshed from Google Patents.
US5349309A
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Second order phase locked loop
Assignee: NEC Electronics Corp
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Filing: 1993-03-31
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Granted: 1994-09-20
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Expires: 2013-03-31
Abstract
Abstract A phase locked loop using an oscillating circuit for controlling the frequency by a digital signal according to the present invention comprises a loop filter. The loop filter includes a random walk filter 3, a counter 4, a register 5 and an adder 6. The oscillating circuit 7 emits a signal having a frequency corresponding to the output of the adder 6. Further, a phase/frequency detector 2 emits a phase lag signal LAG and a phase lead signal LEAD according to the phase difference between a signal IN provided to an input terminal 1 and a signal REF provided from the oscillating circuit 7 to thereby increase the degree of freedom for determining a loop constant while avoiding generation of the steady phase error relative to the frequency offset.
Inventors
- 👤 Takashi Fujii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:46
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
159 words
A phase locked loop comprising: a voltage control oscillating circuit; a phase/frequency detector for comparing an input signal input to a first input terminal of said detector and an output signal of said voltage control oscillating circuit input to a second input terminal of said detector to determine a difference in phase and frequency between said input and output signals, and outputting a detector output signal indicative thereof; a random walk filter for selectively providing one of an up pulse and down pulse in response to the detector output signal; a counter for counting occurrences of said up pulse and down pulse and outputting a count value signal; a register for providing a value signal in response to said detector output signal; and an adder for adding said count value signal and said value signal and outputting and adder output signal, said voltage control oscillating circuit outputting said output signal having a frequency based on said adder output signal.
Claim 2
Dependent Claim
159 words
A phase locked loop comprising: a voltage control oscillating circuit; a phase/frequency detector for comparing an input signal input to a first input terminal of said detector and an output signal of said voltage control oscillating circuit input to a second input terminal of said detector to determine a difference in phase and frequency between said input and output signals, and outputting a detector output signal indicative thereof; a random walk filter for selectively providing one of an up pulse and down pulse in response to the detector output signal; a counter for counting occurrences of said up pulse and down pulse and outputting a count value signal; a register for providing a value signal in response to said detector output signal; and an adder for adding said count value signal and said value signal and outputting and adder output signal, said voltage control oscillating circuit outputting said output signal having a frequency based on said adder output signal.
Claim 3
Dependent Claim
19 words
A phase locked loop as claimed in claim 1, wherein said voltage control oscillating circuit comprises a quartz-crystal resonator.
Claim 4
Dependent Claim
419 words
A phase locked loop comprising: a digitally controlled oscillating circuit having an input and output terminal; a phase/frequency detector for comparing an input signal supplied to a first input terminal of the detector with an oscillator output signal provided at the output terminal of the oscillating circuit and supplied to a second input terminal of the detector to determine the difference in phase and frequency between the input and output signals; a random walk filter for selectively generating an up pulse and a down pulse in response to an output signal provided at an output terminal of the detector and supplied to an input terminal of the filter; a counter for counting occurrences of the up pulse and the down pulse provided at an output terminal of the filter and supplied to an input terminal of the counter to generate a first digital output signal at an output terminal of the counter based on a result of the counting; a register for generating a second digital output signal at an output terminal of the register in response to the output signal provided at the output terminal of the detector and supplied to an input temrinal of the register; an adder for adding the first digital output signal supplied to a first input terminal of the adder to the second digital output signal supplied to a second input terminal of the adder to generate a digital output signal at an output terminal of the adder based on a result of the adding; means for coupling the output terminal of the detector to the input terminal of the filter; means for coupling the output terminal of the filter to the input terminal of the counter; means for coupling the output terminal of the detector to the input terminal of the register; means for coupling the output terminal of the counter to the first input terminal of the adder; means for coupling the output terminal of the register to the second input terminal of the adder; means for coupling the output terminal of the adder to the input terminal of the oscillating circuit; and means for coupling the output terminal of oscillating circuit to the second input terminal of the detector; wherein the digital output signal provided by the adder is supplied to the input terminal of the oscillating circuit, which generates the oscillator output signal having a frequency based on the digital output signal of the adder, the oscillator output signal being supplied to the second input terminal of the detector.
Claim 5
Dependent Claim
419 words
A phase locked loop comprising: a digitally controlled oscillating circuit having an input and output terminal; a phase/frequency detector for comparing an input signal supplied to a first input terminal of the detector with an oscillator output signal provided at the output terminal of the oscillating circuit and supplied to a second input terminal of the detector to determine the difference in phase and frequency between the input and output signals; a random walk filter for selectively generating an up pulse and a down pulse in response to an output signal provided at an output terminal of the detector and supplied to an input terminal of the filter; a counter for counting occurrences of the up pulse and the down pulse provided at an output terminal of the filter and supplied to an input terminal of the counter to generate a first digital output signal at an output terminal of the counter based on a result of the counting; a register for generating a second digital output signal at an output terminal of the register in response to the output signal provided at the output terminal of the detector and supplied to an input temrinal of the register; an adder for adding the first digital output signal supplied to a first input terminal of the adder to the second digital output signal supplied to a second input terminal of the adder to generate a digital output signal at an output terminal of the adder based on a result of the adding; means for coupling the output terminal of the detector to the input terminal of the filter; means for coupling the output terminal of the filter to the input terminal of the counter; means for coupling the output terminal of the detector to the input terminal of the register; means for coupling the output terminal of the counter to the first input terminal of the adder; means for coupling the output terminal of the register to the second input terminal of the adder; means for coupling the output terminal of the adder to the input terminal of the oscillating circuit; and means for coupling the output terminal of oscillating circuit to the second input terminal of the detector; wherein the digital output signal provided by the adder is supplied to the input terminal of the oscillating circuit, which generates the oscillator output signal having a frequency based on the digital output signal of the adder, the oscillator output signal being supplied to the second input terminal of the detector.
Claim 6
Dependent Claim
17 words
A phase locked loop as claimed in claim 3, wherein the oscillating circuit comprises a quartz-crystal resonator.
References Cited (Backward Citations)
US5057794A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-19 | 1998-03-21 | 1998-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-19 | 2002-03-21 | 2002-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-19 | 2006-03-21 | 2006-09-20 | $7700.00 | Window Closed / Lapsed |