Latch controlled output driver

Claim 2

A latch controlled output driver circuit comprising: an output driver circuit including a pull-up transistor and a pull-down transistor, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage; a first latch circuit having an input and an output, wherein the output of the first latch circuit is connected to a gate of the pull-up transistor; a second latch circuit having an input and an output, wherein the output of the second latch circuit is connected to a gate of the pull-down transistor; a first gate having an output connected to the input of the first latch circuit; a second gate having an output connected to the input of the second latch circuit; a first control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the first latch circuit, and a gate connected to the input of the second latch circuit; and a second control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the second latch circuit, and a gate connected to the input of the first latch circuit.

Claim 3

The latch controlled output driver circuit of claim 1, wherein the first gate has an input connected to a true data line and the second gate has an input connected to a complement data line.

Claim 4

The latch controlled output driver circuit of claim 2, wherein the first and second control transistors are p-channel MOSFETs.

Claim 5

The latch controlled output driver circuit of claim 3, wherein the pull-up transistor and the pull-down transistor are n-channel MOSFETs.

Claim 6

The latch controlled output driver circuit of claim 1, wherein the gates are controlled by a clock signal.

Claim 7

The latch controlled output driver circuit of claim 1, wherein the first latch circuit includes a first inverter and a second inverter, the input of the first latch circuit being connected to an input of the first inverter and an output of the second inverter and the output of the first latch circuit being connected to the output of the first inverter and the input of the second inverter and wherein the second latch circuit includes a third inverter and a fourth inverter, the input of the second latch circuit being connected to the input of the third inverter and the output of the fourth inverter and the output of the second latch circuit being connected to the output of the third inverter and the input of the fourth inverter.

Claim 8

The latch controlled output driver circuit of claim 1, wherein the first latch circuit comprises a first inverter, second inverter, a third inverter, and a fourth inverter connected in series, wherein the input of the first latch circuit is connected to an input of the first inverter and an output of the fourth inverter and the output of the first latch circuit being connected to an output of the second inverter and an input of the third inverter.

Claim 9

The latch controlled output driver circuit of claim 1, wherein the first and second gates are pass gates.

Claim 10

A memory comprising: a plurality of memory groups having a plurality of outputs; and a data bus circuit having a plurality of inputs connected the plurality of outputs, the data bus circuit having a latch controlled output driver circuit that includes: an output driver circuit including a pull-up transistor and a pull-down transistor, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage; a first latch circuit having an input and an output, wherein the output of the first latch circuit is connected to a gate of the pull-up transistor; a second latch circuit having an input and an output, wherein the output of the second latch circuit is connected to a gate of the pull-down transistor; a first gate having an output connected to the input of the first latch circuit; a second gate having an output connected to the input of the second latch circuit; a first control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the first latch circuit, and a gate connected to the input of the second latch circuit; and a second control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the second latch circuit, and a gate connected to the input of the first latch circuit.

Claim 11

A memory comprising: a plurality of memory groups having a plurality of outputs; and a data bus circuit having a plurality of inputs connected the plurality of outputs, the data bus circuit having a latch controlled output driver circuit that includes: an output driver circuit including a pull-up transistor and a pull-down transistor, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage; a first latch circuit having an input and an output, wherein the output of the first latch circuit is connected to a gate of the pull-up transistor; a second latch circuit having an input and an output, wherein the output of the second latch circuit is connected to a gate of the pull-down transistor; a first gate having an output connected to the input of the first latch circuit; a second gate having an output connected to the input of the second latch circuit; a first control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the first latch circuit, and a gate connected to the input of the second latch circuit; and a second control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the second latch circuit, and a gate connected to the input of the first latch circuit.

Claim 12

The memory of claim 9, wherein the first gate has an input connected to a true data line and the second gate has an input connected to a complement data line.

Claim 13

The memory of claim 10, wherein the first and second control transistors are p-channel MOSFETs.

Claim 14

The memory of claim 11, wherein the pull-up transistor and the pull-down transistor are n-channel MOSFETs.

Claim 15

The memory of claim 12, wherein the gates are controlled by a clock signal.

Claim 16

The memory of claim 12, wherein the first latch circuit includes a first inverter and a second inverter, the input of the first latch circuit being connected to an input of the first inverter and an output of the second inverter and the output of the first latch circuit being connected to the output of the first inverter and the input of the second inverter and wherein the second latch circuit includes a third inverter and a fourth inverter, the input of the second latch circuit being connected to the input of the third inverter and the output of the fourth inverter and the output of the second latch circuit being connected to the output of the third inverter and the input of the fourth inverter.

Claim 17

The memory of claim 12, wherein the first latch circuit comprises a first inverter, second inverter, a third inverter, and a fourth inverter connected in series, wherein the input of the first latch circuit is connected to an input of the first inverter and an output of the fourth inverter and the output of the first latch circuit being connected to an output of the second inverter and an input of the third inverter.

Claim 18

The memory of claim 9, wherein the first and second gates are pass gates.

Claim 19

A control circuit for controlling first and second output transistors in a driver circuit comprising: first and second latches, each latch having an output and an input, the first latch having an output connected to a gate of the first output transistor, and the second latch having an output connected to a gate of the second output transistor; first and second gates, each gate having an output and an input, the output of the first gate being connected to the input of the first latch and the output of the second gate being connected to the input of the second latch; and a regulation circuit connected to the latch inputs for preventing both inputs from simultaneously having a selected state, wherein the selected state at a latch inputs causes a corresponding output transistor to be turned on.

Claim 20

A control circuit for controlling first and second output transistors in a driver circuit comprising: first and second latches, each latch having an output and an input, the first latch having an output connected to a gate of the first output transistor, and the second latch having an output connected to a gate of the second output transistor; first and second gates, each gate having an output and an input, the output of the first gate being connected to the input of the first latch and the output of the second gate being connected to the input of the second latch; and a regulation circuit connected to the latch inputs for preventing both inputs from simultaneously having a selected state, wherein the selected state at a latch inputs causes a corresponding output transistor to be turned on.

Claim 21

The control circuit of claim 17, wherein the regulation circuit comprises: a first regulation transistor having a source connected to an upper power supply voltage, a drain connected to the input of the first latch circuit, and a gate connected to the input of the second latch circuit; and a second regulation transistor having a source connected to the upper power supply voltage, a drain connected to the input of the second latch circuit, and a gate connected to the input of the first latch circuit.

Claim 22

The control circuit of claim 18, wherein the first and second regulation transistors are p-channel transistors.

Claim 23

The control circuit of claim 19, wherein the sources of the first and second regulation transistors are connected to a positive upper power supply voltage.

Claim 24

The control circuit of claim 17, wherein the first and second gates are pass gates.