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Patent US5347642A successfully refreshed from Google Patents.
US5347642A
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Cache memory management unit
Assignee: Renesas Electronics America Inc
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Filing: 1989-11-30
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Granted: 1994-09-13
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Expires: 2009-11-30
Abstract
Abstract A cache memory management unit that performs searches in a cache memory unit that supplements a disc memory that serves a digital computer. When the computer needs to write a chosen data block into, or read a chosen data block from, its disc memory, the unit first performs a search for the tag or identification label for the chosen data block in the cache memory unit, before the computer searches the disc memory. The unit also implements an algorithm that identifies the least recently used and most recently used cache data blocks.
Inventors
- 👤 Peter G. Barratt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:13
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/12; G06F12/121; G06F12/123; G06F12/0802; G06F12/0866
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
275 words
In a digital computer, a cache memory management apparatus for a cache memory holding copies of selected data blocks of a disc memory, said apparatus comprising: a cache tag register containing K f tag positions, number k=0, 1, 2, . . . , K f 1, where K f is a positive integer, each tag position containing an N-bit disk data location tag, corresponding to the location in disk memory of a selected data block, and an M-bit tag pointer, corresponding to the location in cache memory at which a copy of said selected data block is held; a comparator circuit, receiving from said digital computer an input disk data location tag, for comparing said input disk data location tag to said disk data location tags at said K f positions of said cache tag register, said comparator circuit including a priority encoder which provides, as an output tag pointer, the tag pointer at the k=p tag position, the k=p tag position being (a) during a read operation, the lowest-numbered tag position that has a disk data location tag matching said disk data location tag from said digital computer, and (b) during a write operation, the highest numbered tag position that has a disk data location tag matching said input disk data location tag; and means for moving (a) by one tag position the contents at each of the tag positions in said cache tag register between the k=0 and the k=p-1 positions to the respective tag positions between the k=1 and the k=p tag positions, and (b) said input disk data location tag and said first output tag pointer to the k=0 tag position.
Claim 2
Dependent Claim
275 words
In a digital computer, a cache memory management apparatus for a cache memory holding copies of selected data blocks of a disc memory, said apparatus comprising: a cache tag register containing K f tag positions, number k=0, 1, 2, . . . , K f 1, where K f is a positive integer, each tag position containing an N-bit disk data location tag, corresponding to the location in disk memory of a selected data block, and an M-bit tag pointer, corresponding to the location in cache memory at which a copy of said selected data block is held; a comparator circuit, receiving from said digital computer an input disk data location tag, for comparing said input disk data location tag to said disk data location tags at said K f positions of said cache tag register, said comparator circuit including a priority encoder which provides, as an output tag pointer, the tag pointer at the k=p tag position, the k=p tag position being (a) during a read operation, the lowest-numbered tag position that has a disk data location tag matching said disk data location tag from said digital computer, and (b) during a write operation, the highest numbered tag position that has a disk data location tag matching said input disk data location tag; and means for moving (a) by one tag position the contents at each of the tag positions in said cache tag register between the k=0 and the k=p-1 positions to the respective tag positions between the k=1 and the k=p tag positions, and (b) said input disk data location tag and said first output tag pointer to the k=0 tag position.
Claim 3
Dependent Claim
105 words
Apparatus according to claim 1, further including a mask register connected to said comparator, to provide an N-bit mask sequence that is received by said comparator together with said input disk data location tag, each bit of the N-bit mask sequence corresponding to a bit in each of the input disk data location tag and said disk data location tags in said cache tag register, such that said comparator compares only the corresponding bits in each disk data location tag of said cache tag register to the corresponding bits of the input disk data location tag not set in the bits of said mask sequence.
Claim 4
Dependent Claim
276 words
In a digital computer, a method for managing a cache memory holding copies of selected data blocks of a disc memory, said method comprising the steps of: providing a cache tag register containing K f tag positions, numbered k=0, 1, 2, . . . , K f -1, where K f is a positive integer, each tag position containing an N-bit disk data location tag, corresponding to the location in disc memory of a selected data block, and an M-bit tag pointer, corresponding to the location in cache memory at which a copy of said selected data block is held; receiving from said digital computer an input disk data location tag; comparing, in a comparator circuit, said input disk data location tag to said disk data location tags at said K f positions of said cache tag register, said comparator circuit including a priority encoder which provides, as an output tag pointer, the tag pointer at the k=p tag position, the k=p tag position being (a) during a read operation, the lowest-numbered tag position that has a disk data location tag matching said disk data location tag from said digital computer, and (b) during a write operation, the highest numbered tag position that has a disk data location tag matching said input disk data location tag; and moving (a) by one tag position the contents at each of the tag positions in said cache tag register between the k=0 and the k=p-1 tag positions to the respective tag positions between the k=1 and the k=p tag positions, and (b) said input disk data location tag and said first output tag pointer to the k=0 tag position.
Claim 5
Dependent Claim
276 words
In a digital computer, a method for managing a cache memory holding copies of selected data blocks of a disc memory, said method comprising the steps of: providing a cache tag register containing K f tag positions, numbered k=0, 1, 2, . . . , K f -1, where K f is a positive integer, each tag position containing an N-bit disk data location tag, corresponding to the location in disc memory of a selected data block, and an M-bit tag pointer, corresponding to the location in cache memory at which a copy of said selected data block is held; receiving from said digital computer an input disk data location tag; comparing, in a comparator circuit, said input disk data location tag to said disk data location tags at said K f positions of said cache tag register, said comparator circuit including a priority encoder which provides, as an output tag pointer, the tag pointer at the k=p tag position, the k=p tag position being (a) during a read operation, the lowest-numbered tag position that has a disk data location tag matching said disk data location tag from said digital computer, and (b) during a write operation, the highest numbered tag position that has a disk data location tag matching said input disk data location tag; and moving (a) by one tag position the contents at each of the tag positions in said cache tag register between the k=0 and the k=p-1 tag positions to the respective tag positions between the k=1 and the k=p tag positions, and (b) said input disk data location tag and said first output tag pointer to the k=0 tag position.
Claim 6
Dependent Claim
109 words
The method of claim 3, further including the step of using a mask register connected to said comparator, to provide an N-bit mask sequence that is received by said comparator together with said input disk data location tag, each bit of the N-bit mask sequence corresponding to a bit in each of the input disk data location tag and said disk data location tags in said cache tag register, such that said comparator compares only the corresponding bits in each disk data location tag of said cache tag register to the corresponding bits of the input disk data location tag not set in the bits of said mask sequence.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |