Encoder arrangement having preventive policing circuit (PPC) with statistical measurement circuit (SMC) and data output rate reduction circuit (CRRC)

Claim 1

Encoder arrangement, comprising: a data source (VSS) for providing data signals (VI); an encoder circuit (ENC), responsive to the data signals (VI), for providing data output signals (TXD3) at a buffer input data rate; a buffer circuit (BUFC), responsive to the data output signals (TXD3), and further responsive to a read-out input signal (RO), for providing buffer output data at a buffer output data rate to an output T o ; and a preventive policing circuit (PPC) for controlling the buffer output data rate as a function of a predetermined probability distribution function (CCCP/CR), having a statistical measurement circuit (SMC) and a data output rate reduction circuit (CRRC), the statistical measurement circuit (SMC) being responsive to the data output signals (TXD3), for measuring the buffer input data rate at the end of each measurement interval, for providing interval signals (SCA/F) indicative of one of a plurality of consecutive data output rate intervals (BRI0/2, 3/4, 5/6, 7/8, 9/10, 11) corresponding to the buffer input data rate for each measurement interval, for also providing a data output rate signal (CRS), and for further providing an alarm signal (AL:O/ALO/3, 1) to indicate whether the data output rate signal (CRS) has to be temporarily decreased during a following measurement interval, and the data output rate reduction circuit (CRRC) being responsive to the interval signals (SCA/F), also being responsive to the alarm signal (A:0/AL0/3, 1) and further being responsive to the data output rate signal (CRS), for providing the readout input signal (RO) to said buffer circuit (BUFC) for reducing the buffer output data rate of the buffer output data from said buffer circuit (BUFC) to the output T o in the following measurement interval.