Patent US1850283A successfully refreshed from Google Patents.
Patent US5347483A successfully refreshed from Google Patents.
US5347483A
Expired / Lapsed
US
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Non-volatile associative memory with low transistor count
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-03-05
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Granted: 1994-09-13
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Expires: 2013-03-05
Abstract
Abstract A non-volatile memory cell is disclosed. The non-volatile memory cell includes first and second selecting transistors, first and second non-volatile memory transistors for storing data in a non-volatile manner, and first and second output transistors. A gate of the first selecting transistor and a gate of the second selecting transistor are connected to a word line. A drain of the first selecting transistor is connected to a first bit line, and a drain of the second selecting transistor is connected to a second bit line. A drain of the first non-volatile memory transistor is connected to a source of the first selecting transistor. A drain of the second non-volatile memory transistor is connected to a source of the second selecting transistor. A source of the first non-volatile memory transistor and a source of the second non-volatile memory transistor are connected to a source line. A gate of the first non-volatile memory transistor and a gate of the second non-volatile memory transistor are connected to a control gate line. A drain of the first output transistor and a drain of the second output transistor are connected to a first output line. A source of the first output transistor and a source of the second output transistor are connected to a second output line. A gate of the first output transistor is connected to a drain of the first non-volatile memory transistor. A gate of the second output transistor is connected to a drain of the second non-volatile memory transistor.
Inventors
- 👤 Yasuo Torimaru
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:44
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G11C15/046
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
243 words
A non-volatile memory cell comprising: first and second selecting transistors, a gate of said first selecting transistor and a gate of said second selecting transistor being connected to a word line, a drain of said first selecting transistor being connected to a first bit line, a drain of said second selecting transistor being connected to a second bit line; first and second non-volatile memory transistors for storing data in a non-volatile manner, a drain of said first non-volatile memory transistor being connected to a source of said first selecting transistor, a drain of said second non-volatile memory transistor being connected to a source of said second selecting transistor, a source of said first non-volatile memory transistor and a source of said second non-volatile memory transistor being connected to a source line, a gate of said first non-volatile memory transistor and a gate of said second non-volatile memory transistor being connected to a control gate line; and first and second output transistors, a drain of said first output transistor and a drain of said second output transistor being directly connected to a first output line, a source of said first output transistor and a source of said second output transistor being directly connected to a second output line, a gate of said first output transistor being connected to a drain of said first non-volatile memory transistor, a gate of said second output transistor being connected to a drain of said second non-volatile memory transistor.
Claim 2
Dependent Claim
243 words
A non-volatile memory cell comprising: first and second selecting transistors, a gate of said first selecting transistor and a gate of said second selecting transistor being connected to a word line, a drain of said first selecting transistor being connected to a first bit line, a drain of said second selecting transistor being connected to a second bit line; first and second non-volatile memory transistors for storing data in a non-volatile manner, a drain of said first non-volatile memory transistor being connected to a source of said first selecting transistor, a drain of said second non-volatile memory transistor being connected to a source of said second selecting transistor, a source of said first non-volatile memory transistor and a source of said second non-volatile memory transistor being connected to a source line, a gate of said first non-volatile memory transistor and a gate of said second non-volatile memory transistor being connected to a control gate line; and first and second output transistors, a drain of said first output transistor and a drain of said second output transistor being directly connected to a first output line, a source of said first output transistor and a source of said second output transistor being directly connected to a second output line, a gate of said first output transistor being connected to a drain of said first non-volatile memory transistor, a gate of said second output transistor being connected to a drain of said second non-volatile memory transistor.
Claim 3
Dependent Claim
25 words
A non-volatile memory cell according to claim 1, wherein said first and second non-volatile memory transistors are N-channel non-volatile memory transistors of floating gate type.
Claim 4
Dependent Claim
255 words
A non-volatile associative memory device including a plurality of memory cells, each of said memory cells comprising: first and second selecting transistors, a gate of said first selecting transistor and a gate of said second selecting transistor being connected to a word line, a drain of said first selecting transistor being connected to a first bit line, a drain of said second selecting transistor being connected to a second bit line; first and second non-volatile memory transistors for storing data in a non-volatile manner, a drain of said first non-volatile memory transistor being connected to a source of said first selecting transistor, a drain of said second non-volatile memory transistor being connected to a source of said second selecting transistor, a source of said first non-volatile memory transistor and a source of said second non-volatile memory transistor being connected to a source line, a gate of said first non-volatile memory transistor and a gate of said second non-volatile memory transistor being connected to a control gate line; and first and second output transistors, a drain of said first output transistor and a drain of said second output transistor being directly connected to a first output line, a source of said first output transistor and a source of said second output transistor being directly connected to a second output line, a gate of said first output transistor being connected to a drain of said first non-volatile memory transistor, a gate of said second output transistor being connected to a drain of said second non-volatile memory transistor.
Claim 5
Dependent Claim
255 words
A non-volatile associative memory device including a plurality of memory cells, each of said memory cells comprising: first and second selecting transistors, a gate of said first selecting transistor and a gate of said second selecting transistor being connected to a word line, a drain of said first selecting transistor being connected to a first bit line, a drain of said second selecting transistor being connected to a second bit line; first and second non-volatile memory transistors for storing data in a non-volatile manner, a drain of said first non-volatile memory transistor being connected to a source of said first selecting transistor, a drain of said second non-volatile memory transistor being connected to a source of said second selecting transistor, a source of said first non-volatile memory transistor and a source of said second non-volatile memory transistor being connected to a source line, a gate of said first non-volatile memory transistor and a gate of said second non-volatile memory transistor being connected to a control gate line; and first and second output transistors, a drain of said first output transistor and a drain of said second output transistor being directly connected to a first output line, a source of said first output transistor and a source of said second output transistor being directly connected to a second output line, a gate of said first output transistor being connected to a drain of said first non-volatile memory transistor, a gate of said second output transistor being connected to a drain of said second non-volatile memory transistor.
Claim 6
Dependent Claim
268 words
A non-volatile associative memory device including a plurality of memory cells, each of said memory cells comprising: first and second selecting transistors, a gate of said first selecting transistor and a gate of said second selecting transistor being connected to a word line, a drain of said first selecting transistor being connected to a first bit line, a drain of said second selecting transistor being connected to a second bit line; first and second non-volatile memory transistors for storing data in a non-volatile manner, a drain of said first non-volatile memory transistor being connected to a source of said first selecting transistor, a drain of said second non-volatile memory transistor being connected to a source of said second selecting transistor, a source of said first non-volatile memory transistor and a source of said second non-volatile memory transistor being connected to a source line, a gate of said first non-volatile memory transistor and a gate of said second non-volatile memory transistor being connected to a control gate line; and first and second output transistors, a drain of said first output transistor and a drain of said second output transistor being connected to a first output line, a source of said first output transistor and a source of said second output transistor being connected to a second output line, a gate of said first output transistor being connected to a drain of said first non-volatile memory transistor, a gate of said second output transistor being connected to a drain of said second non-volatile memory transistor, wherein said memory cells are connected in series via said first and second output lines.
Claim 7
Dependent Claim
268 words
A non-volatile associative memory device including a plurality of memory cells, each of said memory cells comprising: first and second selecting transistors, a gate of said first selecting transistor and a gate of said second selecting transistor being connected to a word line, a drain of said first selecting transistor being connected to a first bit line, a drain of said second selecting transistor being connected to a second bit line; first and second non-volatile memory transistors for storing data in a non-volatile manner, a drain of said first non-volatile memory transistor being connected to a source of said first selecting transistor, a drain of said second non-volatile memory transistor being connected to a source of said second selecting transistor, a source of said first non-volatile memory transistor and a source of said second non-volatile memory transistor being connected to a source line, a gate of said first non-volatile memory transistor and a gate of said second non-volatile memory transistor being connected to a control gate line; and first and second output transistors, a drain of said first output transistor and a drain of said second output transistor being connected to a first output line, a source of said first output transistor and a source of said second output transistor being connected to a second output line, a gate of said first output transistor being connected to a drain of said first non-volatile memory transistor, a gate of said second output transistor being connected to a drain of said second non-volatile memory transistor, wherein said memory cells are connected in series via said first and second output lines.
Claim 8
Dependent Claim
24 words
A non-volatile associative memory device according to claim 3, wherein said memory cells are connected in parallel via said first and second output lines.
Claim 9
Dependent Claim
27 words
A non-volatile associative memory device according to claim 4, wherein said first and second non-volatile memory transistors are N-channel non-volatile memory transistors of a floating gate type.
Claim 10
Dependent Claim
35 words
A non-volatile associative memory device according to claim 4, wherein said first and second selecting transistors, said first and second non-volatile memory transistors, and said first and second output transistors have a same type polarity.
Claim 11
Dependent Claim
34 words
A non-volatile associative memory device according to claim 7, wherein said first and second selecting transistors, said first and second non-volatile memory transistors, and said first and second output transistors are each N-channel transistors.
References Cited (Backward Citations)
US4460978A
Cited
JPS63266697A
Cited
JPH01184790A
Cited
JPH01192089A
Cited
JPH01194196A
Cited
JPH0278098A
Cited
US5051948A
Cited
JPH01307095A
Cited
JPH0235690A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |