US5346587A
Expired / Lapsed
US
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Planarization of a gate electrode for improved gate patterning over non-planar active area isolation
Assignee: Round Rock Research LLC
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Filing: 1993-08-12
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Granted: 1994-09-13
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Expires: 2013-08-12
Abstract
Abstract The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.
Inventors
- 👤 Trung T. Doan
- 👤 Charles H. Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:06
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/062
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
68 words
A process for providing a planarized conductor on a non-planar starting substrate, said process comprising the steps of: forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said conductive material extends above the topology of said isolation regions; forming a layer of reflective material superjacent and coextensive said planarized conductive material; and patterning said conductive material thereby forming said planarized conductor.
Claim 2
Dependent Claim
68 words
A process for providing a planarized conductor on a non-planar starting substrate, said process comprising the steps of: forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said conductive material extends above the topology of said isolation regions; forming a layer of reflective material superjacent and coextensive said planarized conductive material; and patterning said conductive material thereby forming said planarized conductor.
Claim 3
Dependent Claim
16 words
The process of claim 1, wherein said reflective material comprises a layer of reflective conductive material.
Claim 4
Dependent Claim
17 words
The process of claim 1, wherein said reflective material comprises a layer of partially reflective insulative material.
Claim 5
Dependent Claim
18 words
The process of claim 1, wherein said layer of planarized conductive material is planarized by chemical mechanical polishing.
Claim 6
Dependent Claim
16 words
The process of claim 1, wherein said layer of planarized conductive material comprises conductively doped polysilicon.
Claim 7
Dependent Claim
24 words
The process of claim 2, wherein said layer of reflective conductive material comprises a material selected from the group of metal silicides and metals.
Claim 8
Dependent Claim
18 words
The process of claim 6, wherein said metal silicides comprise the group of tungsten silicide and titanium silicide.
Claim 9
Dependent Claim
13 words
The process of claim 3, wherein said partially reflective insulating material comprises nitride.
Claim 10
Dependent Claim
73 words
A process for providing a planarized transistor gate on a non-planar starting substrate, said process comprising the steps of: forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said conductive material extends above the topology of said isolation regions; forming a layer of reflective material superjacent and coextensive said planarized conductive material; and patterning said conductive material thereby forming said thereby forming said planarized transistor gate.
Claim 11
Dependent Claim
73 words
A process for providing a planarized transistor gate on a non-planar starting substrate, said process comprising the steps of: forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said conductive material extends above the topology of said isolation regions; forming a layer of reflective material superjacent and coextensive said planarized conductive material; and patterning said conductive material thereby forming said thereby forming said planarized transistor gate.
Claim 12
Dependent Claim
15 words
The process of claim 9, wherein said layer of reflective material comprises reflective conductive material.
Claim 13
Dependent Claim
17 words
The process of claim 9, wherein said reflective material comprises a layer of partially reflective insulative material.
Claim 14
Dependent Claim
18 words
The process of claim 9, wherein said layer of planarized conductive material is planarized by chemical mechanical polishing.
Claim 15
Dependent Claim
16 words
The process of claim 9, wherein said layer of planarized conductive material comprises conductively doped polysilicon.
Claim 16
Dependent Claim
24 words
The process of claim 10, wherein said layer of reflective conductive material comprises a material selected from the group of metal silicides and metals.
Claim 17
Dependent Claim
18 words
The process of claim 14, wherein said metal silicides comprise the group of tungsten silicide and titanium silicide.
Claim 18
Dependent Claim
13 words
The process of claim 11, wherein said partially reflective insulating material comprises nitride.
Claim 19
Dependent Claim
17 words
The process of claim 9, wherein said layer of planarized conductive material comprises in-situ conductively doped polysilicon.
Claim 20
Dependent Claim
17 words
The process of claim 9, wherein said layer of planarized conductive polysilicon material is approximately 3000Å thick.
Claim 21
Dependent Claim
23 words
The process of claim 9, wherein said layer of planarized conductive polysilicon material has a thickness of approximately 1000Å overlying said field oxide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |