High density nonvolatile memory and decoder of the same

Claim 2

A non-volatile memory device comprising: a plurality of non-volatile read/write memory cells (M) arranged in a matrix configuration (WB) and including floating gate type MIS transistors to be programmed to a high threshold voltage or to a low threshold voltage in accordance with programmed data to be written; a plurality of word lines (W 1 to W n ) used in common in each row of said memory cells (M) and functioning as gates of said MIS transistors; a row selection means having outputs connected to said word lines to select one of said word lines (W 1 to Wn) and to modify voltage levels of said word lines (W l to W n ) for selectively programming said memory cells; a plurality of sub-bit lines (B12, B21, B22, B31) arranged substantially orthogonally to said word lines (W 1 to W n ), wherein said sub-bit lines (B12, B21, B22, B31) function as one of the sources or the drains of said MIS transistors and are used in common by one of adjacent columns of said memory cells (M), and are formed as diffusion regions by introducing impurities of an opposite conductivity type into a substrate surface; a plurality of sub-column lines (C11, C12, C21, C22) arranged between said sub-bit lines (B12, B21, B22, B31), wherein said sub-column lines (C11, C12, C21, C22) are used in common by the other of adjacent sub-columns of said memory cells (M) and function as the other of said sources or drains of said MIS transistors of columns of said memory cells (M), and are formed as diffusion regions by introducing impurities of an opposite conductivity type into a substrate surface; characterized in that: first selection means (1) is arranged for selecting groups each consisting of a plurality of said sub-bit lines (B12, B21, B22, B31) and a plurality of said sub-column lines (C11, C12, C21, C22); second selection means (2) is arranged for selecting said sub-bit lines (B12, B21, B22, B31) in each group and to connect said sub-bit lines (B12, B21, B22, B31) to main-bit lines (B1, B2, B3); and third selection means (3) is arranged for selecting said sub-column lines (C11, C12, C21, C22) in each group and to connect said sub-column lines (C11, C12, C21, C22) to main-column lines (C1, C2).

Claim 3

A device according to claim 1 wherein said second and third selection means (2, 3) comprise insulated gate field effect transistors.

Claim 4

A device according to claim 1 wherein said second and third selection means (2, 3) comprise insulated gate field effect transistors of the same conductivity type as said MIS transistors.

Claim 5

A device according to claim 2 or claim 3 wherein said sub-bit lines (B12, B21, B22, B31) and said sub-column lines (C11, C12, C21, C22) are formed in a striped pattern on a substrate and in a direction substantially orthogonal to the longitudinal direction of said insulated gate field effect transistors of said second and third selection means (2, 3).

Claim 6

A device according to claim 1 wherein said second selection means (2) is arranged in opposition to said third selection means (3) with an array of said memory cells (M) between.

Claim 7

A device according to claim 1 wherein said memory cells (M) in the matrix configuration (MB) are divided into blocks along the sub-bit lines (B12, B21, B22, B31) and wherein said first selection means (1) is used in common in each block.

Claim 9

A device according to claim 7 wherein said memory cells (M) in matrix configuration (MB) are divided into blocks along the bit lines (B1, B2, B3), and wherein the load circuits (4) are used in common by each block.

Claim 11

A device according to claim 9 wherein said main-bit lines (B1, B2, B3) and said main-column lines (C1, C2) are made of metal or other low resistance material.

Claim 12

A non-volatile memory device comprising: a plurality of non-volatile read/write memory cells (M) arranged in a matrix configuration (WB) and including floating gate type MIS transistors, and wherein said memory cells (M) are divided into a plurality of blocks along main-bit lines (B1, B2, B3); a plurality of word lines (W 1 to W n ) used in common in each row of said memory cells (M) and functioning as gates of said MIS transistors; a row selection means having outputs connected to said word lines to select one of said word lines (W 1 to W n ) and to modify voltage levels of said word lines (W 1 to W n ) for selectively writing into said memory cells; a plurality of sub-bit lines (B12, B21, B22, B31) arranged substantially orthogonally to said word lines (W 1 to W n ), wherein said sub-bit lines (B12, B21, B22, B31) function as one of the sources or the drains of said MIS transistors and are used in common by one of adjacent columns of said memory cells (M), and are formed as diffusion regions by introducing impurities of an opposite conductivity type into a substrate surface; and a plurality of sub-column lines (C11, C12, C21, C22) arranged between said sub-bit lines (B12, B21, B22, B31), in alternation with and parallel to said bit lines (B1, B2, B3), wherein said sub-column lines (C11, C12, C21, C22) are used in common by the other of adjacent sub-columns of said memory cells (M) and function as the other of said sources or drains of said MIS transistors of columns of said memory cells (M), and are formed as diffusion regions by introducing impurities of an opposite conductivity type into a substrate surface; characterized in that: first selection means (1) is arranged for selecting groups each consisting of a plurality of said sub-bit lines (B12, B21, B22, B31) and a plurality of said sub-column lines (C11, C12, C21, C22) in common in each block; second selection means (2) is arranged for selecting said sub-bit lines (B12, B21, B22, B31) in each group to connect said sub-bit lines (B12, B21, B22, B31) to main-bit lines (B1, B2, B3); third selection means (3) is arranged for selecting said sub-column lines (C11, C12, C21, C22) in each group and to connect said sub-column lines (C11, C12, C21, C22) to main-column lines (C1, C2); load circuits (4) are arranged at terminal ends of each main-bit line (B1, B2, B3) and each main-column line (B. C) (C1, C2); and fourth selection means is provided for selecting one of said blocks; wherein one of said blocks is selected said second selection means (2) and said third selection means (3) in said one of said blocks.

Claim 13

A non-volatile memory device comprising: a plurality of non-volatile read/write memory cells (M) arranged in a matrix configuration (WB) and including floating gate type MIS transistors, and wherein said memory cells (M) are divided into a plurality of blocks along main-bit lines (B1, B2, B3); a plurality of word lines (W 1 to W n ) used in common in each row of said memory cells (M) and functioning as gates of said MIS transistors; a row selection means having outputs connected to said word lines to select one of said word lines (W 1 to W n ) and to modify voltage levels of said word lines (W 1 to W n ) for selectively writing into said memory cells; a plurality of sub-bit lines (B12, B21, B22, B31) arranged substantially orthogonally to said word lines (W 1 to W n ), wherein said sub-bit lines (B12, B21, B22, B31) function as one of the sources or the drains of said MIS transistors and are used in common by one of adjacent columns of said memory cells (M), and are formed as diffusion regions by introducing impurities of an opposite conductivity type into a substrate surface; and a plurality of sub-column lines (C11, C12, C21, C22) arranged between said sub-bit lines (B12, B21, B22, B31), in alternation with and parallel to said bit lines (B1, B2, B3), wherein said sub-column lines (C11, C12, C21, C22) are used in common by the other of adjacent sub-columns of said memory cells (M) and function as the other of said sources or drains of said MIS transistors of columns of said memory cells (M), and are formed as diffusion regions by introducing impurities of an opposite conductivity type into a substrate surface; characterized in that: first selection means (1) is arranged for selecting groups each consisting of a plurality of said sub-bit lines (B12, B21, B22, B31) and a plurality of said sub-column lines (C11, C12, C21, C22) in common in each block; second selection means (2) is arranged for selecting said sub-bit lines (B12, B21, B22, B31) in each group to connect said sub-bit lines (B12, B21, B22, B31) to main-bit lines (B1, B2, B3); third selection means (3) is arranged for selecting said sub-column lines (C11, C12, C21, C22) in each group and to connect said sub-column lines (C11, C12, C21, C22) to main-column lines (C1, C2); load circuits (4) are arranged at terminal ends of each main-bit line (B1, B2, B3) and each main-column line (B. C) (C1, C2); and fourth selection means is provided for selecting one of said blocks; wherein one of said blocks is selected said second selection means (2) and said third selection means (3) in said one of said blocks.

Claim 14

A device according to claim 11 wherein said fourth selection means selects the second selection means (2), and the third selection means (3) belonging to one of said blocks.

Claim 15

A device according to claim 11 wherein said fourth selection means selects all said word lines (W1 to Wn) belonging to one of said blocks.

Claim 16

A device according to claim 12 wherein said word lines (W1 to Wn) are used in common in each block.

Claim 17

A device according to claim 11 wherein control signals (WBS, WBS) of said second selection means (2) and control signals (WCS, WCS) of said third selection means (3) are used in common in each blocks.

Claim 18

A device according to claim 11 wherein said main-bit lines (B1, B2, B3) and said main-column lines (C1, C2) ape formed overlying said sub-bit lines (B12, B21, B22, B31).

Claim 19

A device according to claim 12 wherein said main-bit lines (B1, B2, B3) and said main-column lines (C1, C2) are made of metal or other low resistance material.