Interference suppression in CDMA systems

Claim 3

The method as recited in claim 1 wherein the symbol rate is T, the processing gain is N, the chip rate is T c =T/N, the predetermined number of samples per symbol is D>1, one filter in the bank is the matched filter, another filter in the bank is the matched filter having the positions of its weights shifted by the integer part of N/D, and each successive filter in the bank, if any, is a shifted version of the prior shifted filter wherein the shift is in correspondence to the integer part.

Claim 6

The method as recited in claim 3 wherein the symbol rate is T, the processing gain is N, the chip rate is T c =T/N, the predetermined number of samples per symbol is D>1, one filter in the bank is the matched filter, another filter in the bank is the matched filter having the positions of its weights shifted by the integer part of N/D, and each successive filter in the bank, if any, is a shifted version of the prior shifted filter wherein the shift is in correspondence to the integer part.

Claim 9

The method as recited in claim 5 wherein the symbol rate is T, the processing gain is N, the chip rate is T c =T/N, the predetermined number of samples per symbol is D>1, the matched filter weights are partitioned by grouping adjacent weights to form a set of groups of contiguous weights, the set having a number of elements equal to the integer part of N/D, plus one if D does not divide N exactly, and wherein one filter in the sub-bank is assigned one of the groups of contiguous weights from the set of contiguous weights, another filter in the sub-bank is assigned another of the groups of contiguous weights from the set of contiguous weights, and each successive sub-filter in the bank, if any, is assigned yet another of the groups of contiguous weights from the set of contiguous weights.

Claim 10

The method as recited in claim 6 wherein each successive delay line arrangement is a permutation of previously selected ones of the delay line arrangements.

Claim 11

The method as recited in claim 7 wherein the symbol rate is T, the processing gain is N, the chip rate is T c =T/N, the predetermined number of samples per symbol is D>1, the matched filter weights are partitioned by grouping adjacent weights to form a set of groups of contiguous weights, the set having a number of elements equal to the integer part of N/D, plus one if D does not divide N exactly, and wherein one filter in the sub-bank is assigned one of the groups of contiguous weights from the set of contiguous weights, another filter in the sub-bank is assigned another of the groups of contiguous weights from the set of contiguous weights, and each successive sub-filter in the bank, if any, is assigned yet another of the groups of contiguous weights from the set of contiguous weights.

Claim 12

The method as recited in claim 9, wherein each successive delay line arrangement is a permutation of previously selected ones of the delay line arrangements.

Claim 19

Circuitry for demodulating an incoming channel signal propagating in a DS/SS CDMA system with a receiver having a given CDMA signature sequence to generate a detected symbol which estimates a transmitted symbol, wherein the signature sequence is also assigned to a corresponding source, the source and receiver being synchronized, wherein the system has a pre-determined processing gain and a concomitant chip rate determined by the processing gain and the symbol rate of the system, and wherein the incoming channel signal is sampled at the chip rate to produce an incoming sampled signal, the circuitry comprising a bank of at least two filters for receiving the incoming sampled signal, each filter in the bank being selected as a cyclically shifted version of the matched filter used to detect the CDMA signature sequence assigned to the receiver, wherein the number of filters in the bank and each filter in the bank are configured with reference to a predetermined number of samples per symbol selected for processing, means, responsive to the bank of filters, for selecting the output of each filter in the bank at the symbol rate to produce a sampled output, means, responsive to the means for selecting, for weighting each sampled output by a coefficient from a set of coefficients selected to minimize the mean square error between the transmitted symbol and the detected symbol to produce a weighted sampled output, and means, responsive to the means for weighting, for summing each weighted sampled output to thereby generate the detected symbol.

Claim 20

Circuitry for demodulating an incoming channel signal propagating in a DS/SS CDMA system with a receiver having a given CDMA signature sequence to generate a detected symbol which estimates a transmitted symbol, wherein the signature sequence is also assigned to a corresponding source, the source and receiver being synchronized, wherein the system has a pre-determined processing gain and a concomitant chip rate determined by the processing gain and the symbol rate of the system, and wherein the incoming channel signal is sampled at the chip rate to produce an incoming sampled signal, the circuitry comprising a bank of at least two filters for receiving the incoming sampled signal, each filter in the bank being selected as a cyclically shifted version of the matched filter used to detect the CDMA signature sequence assigned to the receiver, wherein the number of filters in the bank and each filter in the bank are configured with reference to a predetermined number of samples per symbol selected for processing, means, responsive to the bank of filters, for selecting the output of each filter in the bank at the symbol rate to produce a sampled output, means, responsive to the means for selecting, for weighting each sampled output by a coefficient from a set of coefficients selected to minimize the mean square error between the transmitted symbol and the detected symbol to produce a weighted sampled output, and means, responsive to the means for weighting, for summing each weighted sampled output to thereby generate the detected symbol.

Claim 21

Circuitry for demodulating an incoming channel signal propagating in a DS/SS CDMA system with a receiver having a given CDMA signature sequence to generate a detected symbol which estimates a transmitted symbol, wherein the signature sequence is also assigned to a corresponding source, the source and receiver being synchronized, wherein the system has a pre-determined processing gain and a concomitant chip rate determined by the processing gain and the symbol rate of the system, and wherein the incoming channel signal is sampled at the chip rate to produce an incoming sampled signal, the circuitry comprising a bank of at least two sub-filters for receiving the incoming sampled signal, each sub-filter in the bank being selected as a partitioned version of the matched filter used to detect the CDMA signature sequence of the receiver, wherein the number of filters in the bank and each sub-filter in the bank are configured with reference to a predetermined number of samples per symbol selected for processing, means, responsive to the bank, for selecting the output of each sub-filter in the bank at an output rate commensurate with the number of filters in the bank to produce a sampled output for each sub-filter and a set of sampled outputs for the bank, means, responsive to said means for selecting, for supplying the set of sampled outputs to a set of tapped delay line arrangements, the number of delay line arrangements being equal to the number of sub-filters, means, responsive to said means for supplying, for selecting for each delay line arrangement predetermined ones of the taps to produce an intermediary signal, means, responsive to said means for selecting, for sampling each intermediary signal at the symbol rate to obtain a sampled intermediary signal, means, responsive to said means for sampling, for weighting each sampled intermediary signal by a coefficient from a set of coefficients selected to minimize the mean square error between the transmitted symbol and the detected symbol to produce a weighted sampled output, and means, responsive to said means for weighting, for summing each weighted sampled output to thereby generate the detected symbol.

Claim 22

Circuitry for demodulating an incoming channel signal propagating in a DS/SS CDMA system with a receiver having a given CDMA signature sequence to generate a detected symbol which estimates a transmitted symbol, wherein the signature sequence is also assigned to a corresponding source, the source and receiver being synchronized, wherein the system has a pre-determined processing gain and a concomitant chip rate determined by the processing gain and the symbol rate of the system, and wherein the incoming channel signal is sampled at the chip rate to produce an incoming sampled signal, the circuitry comprising a bank of at least two sub-filters for receiving the incoming sampled signal, each sub-filter in the bank being selected as a partitioned version of the matched filter used to detect the CDMA signature sequence of the receiver, wherein the number of filters in the bank and each sub-filter in the bank are configured with reference to a predetermined number of samples per symbol selected for processing, means, responsive to the bank, for selecting the output of each sub-filter in the bank at an output rate commensurate with the number of filters in the bank to produce a sampled output for each sub-filter and a set of sampled outputs for the bank, means, responsive to said means for selecting, for supplying the set of sampled outputs to a set of tapped delay line arrangements, the number of delay line arrangements being equal to the number of sub-filters, means, responsive to said means for supplying, for selecting for each delay line arrangement predetermined ones of the taps to produce an intermediary signal, means, responsive to said means for selecting, for sampling each intermediary signal at the symbol rate to obtain a sampled intermediary signal, means, responsive to said means for sampling, for weighting each sampled intermediary signal by a coefficient from a set of coefficients selected to minimize the mean square error between the transmitted symbol and the detected symbol to produce a weighted sampled output, and means, responsive to said means for weighting, for summing each weighted sampled output to thereby generate the detected symbol.

Claim 23

Circuitry for demodulating an incoming channel signal propagating in a DS/SS CDMA system with a receiver having a given CDMA signature sequence to generate a detected symbol which estimates a transmitted symbol, wherein the signature sequence is also assigned to a corresponding source, the source and receiver being synchronized, wherein the system has a pre-determined processing gain and a concomitant chip rate determined by the processing gain and the symbol rate of the system, and wherein the incoming channel signal is sampled at the chip rate to produce an incoming sampled signal, the circuitry comprising a filter matched to the CDMA signature sequence of the receiver for receiving the incoming sampled signal, means, responsive to said filter, for selecting the output of the matched filter at an output rate exceeding the symbol rate to produce a sampled output, means, responsive to said means for selecting, for supplying the set of sampled output to a tapped delay line wherein the number of taps is selected with reference to the output rate, means, responsive to said means for supplying, for weighting each output from a tap with a coefficient from a set of coefficients selected to minimize the mean square error between the transmitted symbol and the detected symbol to produce a weighted sampled output, and means, responsive to said means for weighting, for summing each weighted sampled output to thereby generate the detected symbol.

Claim 24

Circuitry for demodulating an incoming channel signal propagating in a DS/SS CDMA system with a receiver having a given CDMA signature sequence to generate a detected symbol which estimates a transmitted symbol, wherein the signature sequence is also assigned to a corresponding source, the source and receiver being synchronized, wherein the system has a pre-determined processing gain and a concomitant chip rate determined by the processing gain and the symbol rate of the system, and wherein the incoming channel signal is sampled at the chip rate to produce an incoming sampled signal, the circuitry comprising a filter matched to the CDMA signature sequence of the receiver for receiving the incoming sampled signal, means, responsive to said filter, for selecting the output of the matched filter at an output rate exceeding the symbol rate to produce a sampled output, means, responsive to said means for selecting, for supplying the set of sampled output to a tapped delay line wherein the number of taps is selected with reference to the output rate, means, responsive to said means for supplying, for weighting each output from a tap with a coefficient from a set of coefficients selected to minimize the mean square error between the transmitted symbol and the detected symbol to produce a weighted sampled output, and means, responsive to said means for weighting, for summing each weighted sampled output to thereby generate the detected symbol.